riscv/rocket-chip
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synced up with supervisor mode state in latest ISA simulator

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Rimas Avizienis
2011-11-14 01:37:20 -08:00
parent 9d3471a569
commit 5b29765917
3 changed files with 10 additions and 10 deletions
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rocket/src/main/scala/dpath_util.scala
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@ -166,9 +166,7 @@ class rocketDpathPCR extends Component
is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); }
is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); }
is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); }
is (PCR_MEMSIZE) { rdata <== Bits(MEMSIZE_PAGES,64); }
is (PCR_COREID) { rdata <== Bits(COREID,64); }
is (PCR_NUMCORES) { rdata <== Bits(NUMCORES,64); }
is (PCR_FROMHOST) { rdata <== Cat(Fill(32, reg_fromhost(31)), reg_fromhost); }
is (PCR_TOHOST) { rdata <== Cat(Fill(32, reg_tohost(31)), reg_tohost); }
is (PCR_K0) { rdata <== reg_k0; }