riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

synced up with supervisor mode state in latest ISA simulator

Browse Source
This commit is contained in:
Rimas Avizienis
2011-11-14 01:37:20 -08:00
parent 9d3471a569
commit 5b29765917
3 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/dpath.scala
View File

@ -158,7 +158,7 @@ class rocketDpath extends Component
UFix(0, VADDR_BITS)))))))))));
when (!io.host.start){
if_reg_pc <== UFix(0, VADDR_BITS); //32'hFFFF_FFFC;
if_reg_pc <== UFix(START_ADDR, VADDR_BITS);
}
when (!io.ctrl.stallf) {
if_reg_pc <== if_next_pc;