diff --git a/uncore/src/main/scala/tilelink2/Bundles.scala b/uncore/src/main/scala/tilelink2/Bundles.scala
index b77313f9..a28a3e7f 100644
--- a/uncore/src/main/scala/tilelink2/Bundles.scala
+++ b/uncore/src/main/scala/tilelink2/Bundles.scala
@@ -25,12 +25,13 @@ object TLMessages
   val Get            = UInt(0) //     .    .
   val PutFullData    = UInt(1) //     .    .
   val PutPartialData = UInt(2) //     .    .
-  val AtomicData     = UInt(3) //     .    .
-  val Hint           = UInt(4) //     .    .
+  val ArithmeticData = UInt(3) //     .    .
+  val LogicalData    = UInt(4) //     .    .
+  val Hint           = UInt(5) //     .    .
   val AccessAck      = UInt(0) //               .    .
   val AccessAckData  = UInt(1) //               .    .
-  val Acquire        = UInt(5) //     .
-  val Probe          = UInt(5) //          .
+  val Acquire        = UInt(6) //     .
+  val Probe          = UInt(6) //          .
   val ProbeAck       = UInt(2) //               .
   val ProbeAckData   = UInt(3) //               .
   val Release        = UInt(4) //               .
@@ -72,7 +73,7 @@ object TLAtomics
 class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params)
 {
   val opcode  = UInt(width = 3)
-  val param   = UInt(width = 4) // amo_opcode || perms || hint
+  val param   = UInt(width = 3) // amo_opcode || perms || hint
   val size    = UInt(width = params.sizeBits)
   val source  = UInt(width = params.sourceBits)  // from
   val address = UInt(width = params.addressBits) // to
@@ -83,7 +84,7 @@ class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params)
 class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params)
 {
   val opcode  = UInt(width = 3)
-  val param   = UInt(width = 4)
+  val param   = UInt(width = 3)
   val size    = UInt(width = params.sizeBits)
   val source  = UInt(width = params.sourceBits)  // to
   val address = UInt(width = params.addressBits) // from
diff --git a/uncore/src/main/scala/tilelink2/Parameters.scala b/uncore/src/main/scala/tilelink2/Parameters.scala
index 34760410..5503b7fe 100644
--- a/uncore/src/main/scala/tilelink2/Parameters.scala
+++ b/uncore/src/main/scala/tilelink2/Parameters.scala
@@ -95,7 +95,8 @@ case class TLManagerParameters(
   regionType:         RegionType.T  = RegionType.UNCACHEABLE,
   // Supports both Acquire+Release+Finish of these sizes
   supportsAcquire:    TransferSizes = TransferSizes.none,
-  supportsAtomic:     TransferSizes = TransferSizes.none,
+  supportsArithmetic: TransferSizes = TransferSizes.none,
+  supportsLogical:    TransferSizes = TransferSizes.none,
   supportsGet:        TransferSizes = TransferSizes.none,
   supportsPutFull:    TransferSizes = TransferSizes.none,
   supportsPutPartial: TransferSizes = TransferSizes.none,
@@ -113,7 +114,8 @@ case class TLManagerParameters(
   // Largest support transfer of all types
   val maxTransfer = List(
     supportsAcquire.max,
-    supportsAtomic.max,
+    supportsArithmetic.max,
+    supportsLogical.max,
     supportsGet.max,
     supportsPutFull.max,
     supportsPutPartial.max).max
@@ -138,7 +140,8 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
   
   // Operation sizes supported by all outward Managers
   val allSupportAcquire    = managers.map(_.supportsAcquire)   .reduce(_ intersect _)
-  val allSupportAtomic     = managers.map(_.supportsAtomic)    .reduce(_ intersect _)
+  val allSupportArithmetic = managers.map(_.supportsArithmetic).reduce(_ intersect _)
+  val allSupportLogical    = managers.map(_.supportsLogical)   .reduce(_ intersect _)
   val allSupportGet        = managers.map(_.supportsGet)       .reduce(_ intersect _)
   val allSupportPutFull    = managers.map(_.supportsPutFull)   .reduce(_ intersect _)
   val allSupportPutPartial = managers.map(_.supportsPutPartial).reduce(_ intersect _)
@@ -163,7 +166,8 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
 
   // Check for support of a given operation at a specific address
   val supportsAcquire    = safety_helper(_.supportsAcquire)    _
-  val supportsAtomic     = safety_helper(_.supportsAtomic)     _
+  val supportsArithmetic = safety_helper(_.supportsArithmetic) _
+  val supportsLogical    = safety_helper(_.supportsLogical)    _
   val supportsGet        = safety_helper(_.supportsGet)        _
   val supportsPutFull    = safety_helper(_.supportsPutFull)    _
   val supportsPutPartial = safety_helper(_.supportsPutPartial) _
@@ -177,7 +181,8 @@ case class TLClientParameters(
   sourceId:            IdRange       = IdRange(0,1),
   // Supports both Probe+Grant of these sizes
   supportsProbe:       TransferSizes = TransferSizes.none,
-  supportsAtomic:      TransferSizes = TransferSizes.none,
+  supportsArithmetic:  TransferSizes = TransferSizes.none,
+  supportsLogical:     TransferSizes = TransferSizes.none,
   supportsGet:         TransferSizes = TransferSizes.none,
   supportsPutFull:     TransferSizes = TransferSizes.none,
   supportsPutPartial:  TransferSizes = TransferSizes.none,
@@ -185,7 +190,8 @@ case class TLClientParameters(
 {
   val maxTransfer = List(
     supportsProbe.max,
-    supportsAtomic.max,
+    supportsArithmetic.max,
+    supportsLogical.max,
     supportsGet.max,
     supportsPutFull.max,
     supportsPutPartial.max).max
@@ -203,7 +209,8 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
 
   // Operation sizes supported by all inward Clients
   val allSupportProbe      = clients.map(_.supportsProbe)     .reduce(_ intersect _)
-  val allSupportAtomic     = clients.map(_.supportsAtomic)    .reduce(_ intersect _)
+  val allSupportArithmetic = clients.map(_.supportsArithmetic).reduce(_ intersect _)
+  val allSupportLogical    = clients.map(_.supportsLogical)   .reduce(_ intersect _)
   val allSupportGet        = clients.map(_.supportsGet)       .reduce(_ intersect _)
   val allSupportPutFull    = clients.map(_.supportsPutFull)   .reduce(_ intersect _)
   val allSupportPutPartial = clients.map(_.supportsPutPartial).reduce(_ intersect _)
@@ -223,7 +230,8 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
 
   // Check for support of a given operation at a specific id
   val supportsProbe      = safety_helper(_.supportsProbe)      _
-  val supportsAtomic     = safety_helper(_.supportsAtomic)     _
+  val supportsArithmetic = safety_helper(_.supportsArithmetic) _
+  val supportsLogical    = safety_helper(_.supportsLogical)    _
   val supportsGet        = safety_helper(_.supportsGet)        _
   val supportsPutFull    = safety_helper(_.supportsPutFull)    _
   val supportsPutPartial = safety_helper(_.supportsPutPartial) _