From 5af98145b9d67f2ca90681edcb81ae71ff0b838a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 30 Apr 2016 17:31:46 -0700 Subject: [PATCH] don't signal bad physical address on TLB miss --- rocket/src/main/scala/tlb.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala index 1559802a..700736c3 100644 --- a/rocket/src/main/scala/tlb.scala +++ b/rocket/src/main/scala/tlb.scala @@ -152,13 +152,12 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) { } val paddr = Cat(io.resp.ppn, UInt(0, pgIdxBits)) - val addr_ok = addrMap.isValid(paddr) val addr_prot = addrMap.getProt(paddr) io.req.ready := state === s_ready - io.resp.xcpt_ld := !addr_ok || !addr_prot.r || bad_va || tlb_hit && !(r_array & tag_cam.io.hits).orR - io.resp.xcpt_st := !addr_ok || !addr_prot.w || bad_va || tlb_hit && !(w_array & tag_cam.io.hits).orR - io.resp.xcpt_if := !addr_ok || !addr_prot.x || bad_va || tlb_hit && !(x_array & tag_cam.io.hits).orR + io.resp.xcpt_ld := bad_va || (!tlb_miss && !addr_prot.r) || (tlb_hit && !(r_array & tag_cam.io.hits).orR) + io.resp.xcpt_st := bad_va || (!tlb_miss && !addr_prot.w) || (tlb_hit && !(w_array & tag_cam.io.hits).orR) + io.resp.xcpt_if := bad_va || (!tlb_miss && !addr_prot.x) || (tlb_hit && !(x_array & tag_cam.io.hits).orR) io.resp.miss := tlb_miss io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(ppnBits-1,0)) io.resp.hit_idx := tag_cam.io.hits