Remove invalidation support from BTB
Validating the target PC in the pipeline is cheaper than maintaining the valid bits and control logic to guarantee the BTB won't ever mispredict branch targets.
This commit is contained in:
Andrew Waterman
parent
663002ec0c
commit
5aa8ef1855
@ -36,15 +36,15 @@ class RAS(nras: Int) {
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pos := nextPos
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}
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def peek: UInt = stack(pos)
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def pop: Unit = when (!isEmpty) {
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def pop(): Unit = when (!isEmpty) {
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count := count - 1
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pos := Mux(Bool(isPow2(nras)) || pos > 0, pos-1, UInt(nras-1))
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}
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def clear: Unit = count := UInt(0)
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def clear(): Unit = count := UInt(0)
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def isEmpty: Bool = count === UInt(0)
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private val count = Reg(init=UInt(0,log2Up(nras+1)))
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private val pos = Reg(init=UInt(0,log2Up(nras)))
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private val count = Reg(UInt(width = log2Up(nras+1)))
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private val pos = Reg(UInt(width = log2Up(nras)))
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private val stack = Reg(Vec(nras, UInt()))
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}
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@ -140,82 +140,80 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val btb_update = Valid(new BTBUpdate).flip
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val bht_update = Valid(new BHTUpdate).flip
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val ras_update = Valid(new RASUpdate).flip
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val invalidate = Bool(INPUT)
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}
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val idxValid = Reg(init=UInt(0, entries))
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val idxs = Mem(entries, UInt(width=matchBits))
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val idxPages = Mem(entries, UInt(width=log2Up(nPages)))
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val tgts = Mem(entries, UInt(width=matchBits))
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val tgtPages = Mem(entries, UInt(width=log2Up(nPages)))
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val pages = Mem(nPages, UInt(width=vaddrBits-matchBits))
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val pageValid = Reg(init=UInt(0, nPages))
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val idxs = Reg(Vec(entries, UInt(width=matchBits)))
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val idxPages = Reg(Vec(entries, UInt(width=log2Up(nPages))))
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val tgts = Reg(Vec(entries, UInt(width=matchBits)))
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val tgtPages = Reg(Vec(entries, UInt(width=log2Up(nPages))))
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val pages = Reg(Vec(nPages, UInt(width=vaddrBits-matchBits)))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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val useRAS = Reg(Vec(entries, Bool()))
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val isJump = Reg(Vec(entries, Bool()))
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val brIdx = Mem(entries, UInt(width=log2Up(fetchWidth)))
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val useRAS = Reg(UInt(width = entries))
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val isJump = Reg(UInt(width = entries))
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val brIdx = Reg(Vec(entries, UInt(width=log2Up(fetchWidth))))
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private def page(addr: UInt) = addr >> matchBits
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private def pageMatch(addr: UInt) = {
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val p = page(addr)
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Vec(pages.map(_ === p)).toBits & pageValid
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Vec(pages.map(_ === p)).toBits
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}
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private def tagMatch(addr: UInt, pgMatch: UInt) = {
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val idx = addr(matchBits-1,0)
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val idxMatch = idxs.map(_ === idx).toBits
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).toBits
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idxValid & idxMatch & idxPageMatch
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val idxMatch = idxs.map(_ === addr(matchBits-1,0))
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR)
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(idxPageMatch zip idxMatch) map { case (p, i) => p && i }
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}
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val r_btb_update = Pipe(io.btb_update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req.bits.addr)
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val hits = tagMatch(io.req.bits.addr, pageHit)
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val hitsVec = tagMatch(io.req.bits.addr, pageHit)
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val hits = hitsVec.toBits
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
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val updateHit = r_btb_update.bits.prediction.valid
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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val nextRepl = Reg(UInt(width = log2Ceil(entries)))
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when (r_btb_update.valid && !updateHit) { nextRepl := Mux(nextRepl === entries-1 && Bool(!isPow2(entries)), 0, nextRepl + 1) }
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val nextPageRepl = Reg(UInt(width = log2Ceil(nPages)))
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val useUpdatePageHit = updatePageHit.orR
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val usePageHit = pageHit.orR
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val doIdxPageRepl = !useUpdatePageHit
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val idxPageRepl = Wire(UInt(width = nPages))
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageRepl = UIntToOH(nextPageRepl)
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit,
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Mux(usePageHit, Cat(pageHit(nPages-2,0), pageHit(nPages-1)), idxPageRepl))
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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val usePageHit = (pageHit & ~idxPageReplEn).orR
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val doTgtPageRepl = !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, idxPageUpdateOH(nPages-2,0) << 1 | idxPageUpdateOH(nPages-1))
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1)))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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val doPageRepl = doIdxPageRepl || doTgtPageRepl
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val pageReplEn = idxPageReplEn | tgtPageReplEn
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idxPageRepl := UIntToOH(Counter(r_btb_update.valid && doPageRepl, nPages)._1)
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when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) {
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val both = doIdxPageRepl && doTgtPageRepl
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val next = nextPageRepl + Mux[UInt](both, 2, 1)
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nextPageRepl := Mux(next >= nPages, next(0), next)
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}
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when (r_btb_update.valid) {
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assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
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val waddr =
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if (updatesOutOfOrder) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
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if (updatesOutOfOrder) Mux(updateHits.reduce(_|_), OHToUInt(updateHits), nextRepl)
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else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)
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// invalidate entries if we stomp on pages they depend upon
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val invalidateMask = Vec.tabulate(entries)(i => (pageReplEn & (idxPagesOH(i) | tgtPagesOH(i))).orR).toBits
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val validateMask = UIntToOH(waddr)
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idxValid := (idxValid & ~invalidateMask) | validateMask
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idxs(waddr) := r_btb_update.bits.pc
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tgts(waddr) := update_target
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idxPages(waddr) := idxPageUpdate
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tgtPages(waddr) := tgtPageUpdate
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useRAS(waddr) := r_btb_update.bits.isReturn
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isJump(waddr) := r_btb_update.bits.isJump
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val mask = UIntToOH(waddr)
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useRAS := Mux(r_btb_update.bits.isReturn, useRAS | mask, useRAS & ~mask)
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isJump := Mux(r_btb_update.bits.isJump, isJump | mask, isJump & ~mask)
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if (fetchWidth == 1) {
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brIdx(waddr) := UInt(0)
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} else {
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@ -223,41 +221,29 @@ class BTB(implicit p: Parameters) extends BtbModule {
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}
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require(nPages % 2 == 0)
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val idxWritesEven = (idxPageUpdateOH & Fill(nPages/2, UInt(1,2))).orR
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val idxWritesEven = !idxPageUpdate(0)
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def writeBank(i: Int, mod: Int, en: Bool, data: UInt) =
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def writeBank(i: Int, mod: Int, en: UInt, data: UInt) =
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for (i <- i until nPages by mod)
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when (en && pageReplEn(i)) { pages(i) := data }
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when (en(i)) { pages(i) := data }
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writeBank(0, 2, Mux(idxWritesEven, doIdxPageRepl, doTgtPageRepl),
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writeBank(0, 2, Mux(idxWritesEven, idxPageReplEn, tgtPageReplEn),
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Mux(idxWritesEven, page(r_btb_update.bits.pc), page(update_target)))
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writeBank(1, 2, Mux(idxWritesEven, doTgtPageRepl, doIdxPageRepl),
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writeBank(1, 2, Mux(idxWritesEven, tgtPageReplEn, idxPageReplEn),
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Mux(idxWritesEven, page(update_target), page(r_btb_update.bits.pc)))
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when (doPageRepl) { pageValid := pageValid | pageReplEn }
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}
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when (io.invalidate) {
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idxValid := 0
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pageValid := 0
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}
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io.resp.valid := hits.orR
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io.resp.bits.taken := io.resp.valid
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io.resp.bits.target := Cat(Mux1H(Mux1H(hits, tgtPagesOH), pages), Mux1H(hits, tgts))
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io.resp.bits.target := Cat(Mux1H(Mux1H(hitsVec, tgtPagesOH), pages), Mux1H(hitsVec, tgts))
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io.resp.bits.entry := OHToUInt(hits)
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io.resp.bits.bridx := brIdx(io.resp.bits.entry)
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if (fetchWidth == 1) {
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io.resp.bits.mask := UInt(1)
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} else {
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// note: btb_resp is clock gated, so the mask is only relevant for the io.resp.valid case
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io.resp.bits.mask := Mux(io.resp.bits.taken, Cat((UInt(1) << brIdx(io.resp.bits.entry))-1, UInt(1)).toSInt,
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SInt(-1)).toUInt
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val isBranch = !Mux1H(hits, isJump)
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val isBranch = !(hits & isJump).orR
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val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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@ -269,7 +255,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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val doPeek = Mux1H(hits, useRAS)
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val doPeek = (hits & useRAS).orR
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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@ -280,9 +266,8 @@ class BTB(implicit p: Parameters) extends BtbModule {
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io.resp.bits.target := io.ras_update.bits.returnAddr
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}
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}.elsewhen (io.ras_update.bits.isReturn && io.ras_update.bits.prediction.valid) {
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ras.pop
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ras.pop()
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}
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}
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when (io.invalidate) { ras.clear }
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}
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}
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@ -81,7 +81,6 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
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btb.io.btb_update := io.cpu.btb_update
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btb.io.bht_update := io.cpu.bht_update
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btb.io.ras_update := io.cpu.ras_update
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btb.io.invalidate := false
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when (!stall && !icmiss) {
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btb.io.req.valid := true
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s2_btb_resp_valid := btb.io.resp.valid
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