finished uncore constant/tilelink data refactor
This commit is contained in:
Henry Cook
parent
56f515c255
commit
5a5f69bfca
2
chisel
2
chisel
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Subproject commit 663b8716aa157a6b82f7f4e4f7cbfeb59c9bc3b5
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Subproject commit 41d48485e1cd454e5b7966a6efaac63ba5656796
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2
rocket
2
rocket
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Subproject commit 47e883edc125488b3354729af2669ec8e4123a8b
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Subproject commit 5bc618bc74bf3dffb11f8a6366299c31bf7a247b
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@ -8,8 +8,8 @@ import ReferenceChipBackend._
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import scala.collection.mutable.HashMap
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import DRAMModel._
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object DummyTopLevelConstants {
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val NTILES = 2
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object DesignSpaceConstants {
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val NTILES = 1
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val NBANKS = 1
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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@ -18,13 +18,31 @@ object DummyTopLevelConstants {
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val NL2_REL_XACTS = 1
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val NL2_ACQ_XACTS = 7
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val NMSHRS = 2
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}
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object MemoryConstants {
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val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 //TODO: How configurable is this really?
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val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
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val PADDR_BITS = 32
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val VADDR_BITS = 43
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val PGIDX_BITS = 13
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val ASID_BITS = 7
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val PERM_BITS = 6
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val MEM_TAG_BITS = 5
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val MEM_DATA_BITS = 128
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val MEM_ADDR_BITS = PADDR_BITS - OFFSET_BITS
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val MEM_DATA_BEATS = 4
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}
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import DummyTopLevelConstants._
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object TileLinkSizeConstants {
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val WRITE_MASK_BITS = 6
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val SUBWORD_ADDR_BITS = 3
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val ATOMIC_OP_BITS = 4
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}
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import DesignSpaceConstants._
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import MemoryConstants._
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import TileLinkSizeConstants._
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object ReferenceChipBackend {
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val initMap = new HashMap[Module, Bool]()
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@ -150,7 +168,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
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io.mem_backup <> mem_serdes.io.narrow
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}
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case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
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case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, mif: MemoryIFConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int, offsetBits: Int)
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class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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{
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@ -164,7 +182,7 @@ class Uncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Module
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val mem_backup = new MemSerializedIO(htif_width)
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val mem_backup_en = Bool(INPUT)
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}
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val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
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val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
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val outmemsys = Module(new OuterMemorySystem(htif_width))
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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@ -250,19 +268,29 @@ class Top extends Module {
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}
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implicit val ln = LogicalNetworkConfiguration(log2Up(NTILES)+1, NBANKS, NTILES+1)
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implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), CACHE_DATA_SIZE_IN_BYTES*8)
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implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
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implicit val tl = TileLinkConfiguration(co = co, ln = ln,
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addrBits = as.paddrBits-OFFSET_BITS,
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clientXactIdBits = log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS),
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masterXactIdBits = 2*log2Up(NMSHRS*NTILES+1),
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dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
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writeMaskBits = WRITE_MASK_BITS,
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, MEM_DATA_BEATS)
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implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
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implicit val uc = UncoreConfiguration(l2, tl, mif, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS)
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val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 38, tl = tl)
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val dc = DCacheConfig(128, 4, ntlb = 8,
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nmshr = NMSHRS, nrpq = 16, nsdq = 17, tl = tl)
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val vic = ICacheConfig(128, 1, tl = tl)
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val hc = hwacha.HwachaConfiguration(vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val ic = ICacheConfig(sets = 128, assoc = 2, ntlb = 8, tl = tl, as = as, btb = BTBConfig(as, 8))
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val dc = DCacheConfig(sets = 128, ways = 4,
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tl = tl, as = as,
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ntlb = 8, nmshr = NMSHRS, nrpq = 16, nsdq = 17,
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reqtagbits = -1, databits = -1)
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val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
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val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
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val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
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val rc = RocketConfiguration(tl, ic, dc, fpu
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//,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
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val rc = RocketConfiguration(tl, as, ic, dc, fpu,
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rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
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)
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val io = new VLSITopIO(HTIF_WIDTH)
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@ -47,7 +47,7 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
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val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
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val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
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}
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val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
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val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR, conf.offsetBits))
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val outmemsys = Module(new FPGAOuterMemorySystem(htif_width))
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val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
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outmemsys.io.incoherent := incoherentWithHtif
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@ -73,6 +73,9 @@ class FPGAUncore(htif_width: Int)(implicit conf: UncoreConfiguration) extends Mo
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htif.io.host.in <> io.host.in
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}
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import MemoryConstants._
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import TileLinkSizeConstants._
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class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extends Module {
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val io = new Bundle {
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val host_in = new DecoupledIO(new HostPacket(htif_width)).flip()
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@ -90,13 +93,21 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend
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val nbanks = 1
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val nmshrs = 2
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implicit val ln = LogicalNetworkConfiguration(log2Up(ntiles)+1, nbanks, ntiles+1)
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implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), CACHE_DATA_SIZE_IN_BYTES*8)
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implicit val as = AddressSpaceConfiguration(PADDR_BITS, VADDR_BITS, PGIDX_BITS, ASID_BITS, PERM_BITS)
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implicit val tl = TileLinkConfiguration(co = co, ln = ln,
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addrBits = as.paddrBits-OFFSET_BITS,
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clientXactIdBits = log2Up(1+8),
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masterXactIdBits = 2*log2Up(2*1+1),
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dataBits = CACHE_DATA_SIZE_IN_BYTES*8,
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writeMaskBits = WRITE_MASK_BITS,
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wordAddrBits = SUBWORD_ADDR_BITS,
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atomicOpBits = ATOMIC_OP_BITS)
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implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
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implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64)
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implicit val uc = UncoreConfiguration(l2, tl, mif, ntiles, nbanks, bankIdLsb = 5, nSCR = 64, offsetBits = OFFSET_BITS)
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val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4, tl = tl)
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val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl)
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val rc = RocketConfiguration(tl, ic, dc, fpu = None,
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val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8))
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val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
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val rc = RocketConfiguration(tl, as, ic, dc, fpu = None,
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fastMulDiv = false)
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val resetSigs = Vec.fill(uc.nTiles){Bool()}
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@ -138,13 +149,14 @@ class ReferenceChip(htif_width: Int)(implicit mif: MemoryIFConfiguration) extend
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io.mem_resp <> uncore.io.mem.resp
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}
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import MemoryConstants._
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class FPGATopIO(htifWidth: Int)(implicit conf: MemoryIFConfiguration) extends TopIO(htifWidth)(conf)
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class FPGATop extends Module {
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val htif_width = 16
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implicit val mif = MemoryIFConfiguration(PADDR_BITS - OFFSET_BITS, 128, 5, 4)
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implicit val mif = MemoryIFConfiguration(MEM_ADDR_BITS, MEM_DATA_BITS, MEM_TAG_BITS, 4)
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val deviceWidth = ROW_WIDTH/mif.dataBits
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implicit val mc = MemoryControllerConfiguration(deviceWidth, (if(deviceWidth == 4) 0 else log2Up(deviceWidth/4)), mif)
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2
uncore
2
uncore
@ -1 +1 @@
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Subproject commit 67589ccca64716a9be5ab94d50854a8827431be7
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Subproject commit 240fdc0ef7e0735d1b31eb8b8c21fc11f1446a11
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