riscv/rocket-chip
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minNum -> minimumNumber (#766)

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Andrew Waterman 2017-06-08 11:12:52 -07:00 committed by GitHub
parent 8cb250cfe6
commit 5a4daebbcc
2 changed files with 3 additions and 3 deletions
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2
riscv-tools

@ -1 +1 @@
Subproject commit 14bbe5a2e5725cf624874f4c5e35e3333287e728 Subproject commit 21113949ff22bd45c6d5928f7b6214c7e0a88bde

4
src/main/scala/tile/FPU.scala
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@ -433,7 +433,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
} }
io.out.valid := valid io.out.valid := valid
io.out.bits.lt := dcmp.io.lt io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in io.out.bits.in := in
} }
@ -502,7 +502,7 @@ class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
val isnan1 = maxType.isNaN(in.bits.in1) val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2) val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isInvalid || (isnan1 && isnan2) val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1 val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4 fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))