From 5a3beca097d272cc4f3f2b14aca1507110ee8fb0 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 28 Jul 2016 19:58:47 -0700
Subject: [PATCH] add RepeatedGetRegression to uncover L2 merged get miss bug

---
 groundtest/src/main/scala/Regression.scala | 53 +++++++++++++++++++++-
 1 file changed, 52 insertions(+), 1 deletion(-)

diff --git a/groundtest/src/main/scala/Regression.scala b/groundtest/src/main/scala/Regression.scala
index 41c330a2..424adf5a 100644
--- a/groundtest/src/main/scala/Regression.scala
+++ b/groundtest/src/main/scala/Regression.scala
@@ -558,6 +558,56 @@ class PutBeforePutBlockRegression(implicit p: Parameters) extends Regression()(p
   io.errored := Bool(false)
 }
 
+class RepeatedGetRegression(implicit p: Parameters) extends Regression()(p) {
+  disableCache()
+
+  val l2params = p.alterPartial({ case CacheName => "L2Bank" })
+  val nSets = l2params(NSets)
+  val nWays = l2params(NWays)
+
+  val (s_idle :: s_put :: s_get :: s_done :: Nil) = Enum(Bits(), 4)
+  val state = Reg(init = s_idle)
+
+  val (put_acq_cnt, put_acq_done) = Counter(state === s_put && io.mem.acquire.fire(), nWays + 1)
+  val (put_gnt_cnt, put_gnt_done) = Counter(state === s_put && io.mem.grant.fire(), nWays + 1)
+  val put_addr = UInt(memStartBlock) + Cat(put_acq_cnt, UInt(0, log2Up(nSets)))
+
+  val (get_acq_cnt, get_acq_done) = Counter(state === s_get && io.mem.acquire.fire(), 2)
+  val (get_gnt_cnt, get_gnt_done) = Counter(state === s_get && io.mem.grant.fire(), 2)
+  val sending = Reg(init = Bool(false))
+
+  when (state === s_idle && io.start) { state := s_put; sending := Bool(true) }
+  when (state === s_put) {
+    when (io.mem.acquire.fire()) { sending := Bool(false) }
+    when (io.mem.grant.fire()) { sending := Bool(true) }
+    when (put_gnt_done) { state := s_get }
+  }
+  when (state === s_get) {
+    when (get_acq_done) { sending := Bool(false) }
+    when (get_gnt_done) { state := s_done }
+  }
+
+  io.mem.acquire.valid := sending
+  io.mem.acquire.bits := Mux(state === s_put,
+    Put(
+      client_xact_id = UInt(0),
+      addr_block = put_addr,
+      addr_beat = UInt(3),
+      data = UInt("hdabb9321")),
+    Get(
+      client_xact_id = get_acq_cnt,
+      addr_block = UInt(memStartBlock),
+      addr_beat = UInt(3)))
+  io.mem.grant.ready := !sending
+
+  val data_mismatch = io.mem.grant.valid && io.mem.grant.bits.hasData() &&
+                      io.mem.grant.bits.data =/= UInt("hdabb9321")
+  assert(!data_mismatch, "RepeatedGetRegression: wrong data back")
+
+  io.finished := state === s_done
+  io.errored := data_mismatch
+}
+
 object RegressionTests {
   def cacheRegressions(implicit p: Parameters) = Seq(
     Module(new PutBlockMergeRegression),
@@ -569,7 +619,8 @@ object RegressionTests {
     Module(new WritebackRegression),
     Module(new PutBeforePutBlockRegression),
     Module(new MixedAllocPutRegression),
-    Module(new ReleaseRegression))
+    Module(new ReleaseRegression),
+    Module(new RepeatedGetRegression))
   def broadcastRegressions(implicit p: Parameters) = Seq(
     Module(new IOGetAfterPutBlockRegression),
     Module(new WriteMaskedPutBlockRegression),