riscv/rocket-chip
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fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions

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This commit is contained in:
Rimas Avizienis 2011-11-17 11:17:37 -08:00
parent 80b4253318
commit 5a322ff00c
2 changed files with 90 additions and 81 deletions
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155
rocket/src/main/scala/ctrl.scala
View File

@ -87,76 +87,76 @@ class rocketCtrl extends Component
{ {
val io = new ioCtrlAll(); val io = new ioCtrlAll();
val fp = // val fp =
ListLookup(io.dpath.inst, // ListLookup(io.dpath.inst,
List(Bool(false)), // List(Bool(false)),
Array( // Array(
FMOVZ -> List(Bool(true)), // FMOVZ -> List(Bool(true)),
FMOVN -> List(Bool(true)), // FMOVN -> List(Bool(true)),
FADD_S -> List(Bool(true)), // FADD_S -> List(Bool(true)),
FSUB_S -> List(Bool(true)), // FSUB_S -> List(Bool(true)),
FMUL_S -> List(Bool(true)), // FMUL_S -> List(Bool(true)),
FDIV_S -> List(Bool(true)), // FDIV_S -> List(Bool(true)),
FSQRT_S -> List(Bool(true)), // FSQRT_S -> List(Bool(true)),
FSGNJ_S -> List(Bool(true)), // FSGNJ_S -> List(Bool(true)),
FSGNJN_S -> List(Bool(true)), // FSGNJN_S -> List(Bool(true)),
FSGNJX_S -> List(Bool(true)), // FSGNJX_S -> List(Bool(true)),
FADD_D -> List(Bool(true)), // FADD_D -> List(Bool(true)),
FSUB_D -> List(Bool(true)), // FSUB_D -> List(Bool(true)),
FMUL_D -> List(Bool(true)), // FMUL_D -> List(Bool(true)),
FDIV_D -> List(Bool(true)), // FDIV_D -> List(Bool(true)),
FSQRT_D -> List(Bool(true)), // FSQRT_D -> List(Bool(true)),
FSGNJ_D -> List(Bool(true)), // FSGNJ_D -> List(Bool(true)),
FSGNJN_D -> List(Bool(true)), // FSGNJN_D -> List(Bool(true)),
FSGNJX_D -> List(Bool(true)), // FSGNJX_D -> List(Bool(true)),
FCVT_L_S -> List(Bool(true)), // FCVT_L_S -> List(Bool(true)),
FCVT_LU_S -> List(Bool(true)), // FCVT_LU_S -> List(Bool(true)),
FCVT_W_S -> List(Bool(true)), // FCVT_W_S -> List(Bool(true)),
FCVT_WU_S -> List(Bool(true)), // FCVT_WU_S -> List(Bool(true)),
FCVT_L_D -> List(Bool(true)), // FCVT_L_D -> List(Bool(true)),
FCVT_LU_D -> List(Bool(true)), // FCVT_LU_D -> List(Bool(true)),
FCVT_W_D -> List(Bool(true)), // FCVT_W_D -> List(Bool(true)),
FCVT_WU_D -> List(Bool(true)), // FCVT_WU_D -> List(Bool(true)),
FCVT_S_L -> List(Bool(true)), // FCVT_S_L -> List(Bool(true)),
FCVT_S_LU -> List(Bool(true)), // FCVT_S_LU -> List(Bool(true)),
FCVT_S_W -> List(Bool(true)), // FCVT_S_W -> List(Bool(true)),
FCVT_S_WU -> List(Bool(true)), // FCVT_S_WU -> List(Bool(true)),
FCVT_D_L -> List(Bool(true)), // FCVT_D_L -> List(Bool(true)),
FCVT_D_LU -> List(Bool(true)), // FCVT_D_LU -> List(Bool(true)),
FCVT_D_W -> List(Bool(true)), // FCVT_D_W -> List(Bool(true)),
FCVT_D_WU -> List(Bool(true)), // FCVT_D_WU -> List(Bool(true)),
FCVT_S_D -> List(Bool(true)), // FCVT_S_D -> List(Bool(true)),
FCVT_D_S -> List(Bool(true)), // FCVT_D_S -> List(Bool(true)),
FEQ_S -> List(Bool(true)), // FEQ_S -> List(Bool(true)),
FLT_S -> List(Bool(true)), // FLT_S -> List(Bool(true)),
FLE_S -> List(Bool(true)), // FLE_S -> List(Bool(true)),
FEQ_D -> List(Bool(true)), // FEQ_D -> List(Bool(true)),
FLT_D -> List(Bool(true)), // FLT_D -> List(Bool(true)),
FLE_D -> List(Bool(true)), // FLE_D -> List(Bool(true)),
FMIN_S -> List(Bool(true)), // FMIN_S -> List(Bool(true)),
FMAX_S -> List(Bool(true)), // FMAX_S -> List(Bool(true)),
FMIN_D -> List(Bool(true)), // FMIN_D -> List(Bool(true)),
FMAX_D -> List(Bool(true)), // FMAX_D -> List(Bool(true)),
MFTX_S -> List(Bool(true)), // MFTX_S -> List(Bool(true)),
MFTX_D -> List(Bool(true)), // MFTX_D -> List(Bool(true)),
MFFSR -> List(Bool(true)), // MFFSR -> List(Bool(true)),
MXTF_S -> List(Bool(true)), // MXTF_S -> List(Bool(true)),
MXTF_D -> List(Bool(true)), // MXTF_D -> List(Bool(true)),
MTFSR -> List(Bool(true)), // MTFSR -> List(Bool(true)),
FLW -> List(Bool(true)), // FLW -> List(Bool(true)),
FLD -> List(Bool(true)), // FLD -> List(Bool(true)),
FSW -> List(Bool(true)), // FSW -> List(Bool(true)),
FSD -> List(Bool(true)), // FSD -> List(Bool(true)),
FMADD_S -> List(Bool(true)), // FMADD_S -> List(Bool(true)),
FMSUB_S -> List(Bool(true)), // FMSUB_S -> List(Bool(true)),
FNMSUB_S -> List(Bool(true)), // FNMSUB_S -> List(Bool(true)),
FNMADD_S -> List(Bool(true)), // FNMADD_S -> List(Bool(true)),
FMADD_D -> List(Bool(true)), // FMADD_D -> List(Bool(true)),
FMSUB_D -> List(Bool(true)), // FMSUB_D -> List(Bool(true)),
FNMSUB_D -> List(Bool(true)), // FNMSUB_D -> List(Bool(true)),
FNMADD_D -> List(Bool(true)) // FNMADD_D -> List(Bool(true))
)); // ));
val id_fp_val :: Nil = fp; // val id_fp_val :: Nil = fp;
val xpr64 = Y; val xpr64 = Y;
val cs = val cs =
@ -253,9 +253,16 @@ class rocketCtrl extends Component
CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y), CFLUSH-> List(Y, BR_N, REN_Y,REN_N,A2_X, A1_X, DW_X, FN_X, M_Y,M_FLA, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,Y),
MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y), MFPCR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_PCR,REN_Y,WEN_N,I_X ,SYNC_N,N,N,Y),
MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y), MTPCR-> List(Y, BR_N, REN_N,REN_Y,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_Y,I_X ,SYNC_N,N,N,Y),
RDTIME-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N) RDTIME-> List(Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_TSC,REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
// Instructions that have not yet been implemented // Instructions that have not yet been implemented
// Faking these for now so akaros will boot
MFFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
MTFSR-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
FLW-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
FLD-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
FSW-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
FSD-> List(Y, BR_N, REN_N,REN_N,A2_X, A1_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N)
/* /*
// floating point // floating point
FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N), FLW-> List(FPU_Y, BR_N, REN_N,REN_Y,A2_SEXT, A1_RS1,DW_XPR,FN_ADD, M_Y,M_FRD, MT_WU,N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N),
@ -366,7 +373,8 @@ class rocketCtrl extends Component
} }
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim) // executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
val illegal_inst = !(id_int_val.toBool || id_fp_val.toBool) || (id_eret.toBool && io.dpath.status(SR_ET).toBool); // val illegal_inst = !(id_int_val.toBool || id_fp_val.toBool) || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET).toBool);
when (reset.toBool || io.dpath.killd) { when (reset.toBool || io.dpath.killd) {
ex_reg_br_type <== BR_N; ex_reg_br_type <== BR_N;
@ -403,7 +411,8 @@ class rocketCtrl extends Component
ex_reg_xcpt_itlb <== id_reg_xcpt_itlb; ex_reg_xcpt_itlb <== id_reg_xcpt_itlb;
ex_reg_xcpt_illegal <== illegal_inst; ex_reg_xcpt_illegal <== illegal_inst;
ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool; ex_reg_xcpt_privileged <== (id_privileged & ~io.dpath.status(SR_S)).toBool;
ex_reg_xcpt_fpu <== id_fp_val.toBool; // ex_reg_xcpt_fpu <== id_fp_val.toBool;
ex_reg_xcpt_fpu <== Bool(false);
ex_reg_xcpt_syscall <== id_syscall.toBool; ex_reg_xcpt_syscall <== id_syscall.toBool;
} }

16
rocket/src/main/scala/dtlb.scala
View File

@ -85,10 +85,10 @@ class rocketDTLB(entries: Int) extends Component
val status_vm = io.cpu.status(SR_VM).toBool // virtual memory enable val status_vm = io.cpu.status(SR_VM).toBool // virtual memory enable
// extract fields from PT permission bits // extract fields from PT permission bits
val ptw_perm_ur = io.ptw.resp_perm(1); val ptw_perm_ur = io.ptw.resp_perm(2);
val ptw_perm_uw = io.ptw.resp_perm(2); val ptw_perm_uw = io.ptw.resp_perm(1);
val ptw_perm_sr = io.ptw.resp_perm(4); val ptw_perm_sr = io.ptw.resp_perm(5);
val ptw_perm_sw = io.ptw.resp_perm(5); val ptw_perm_sw = io.ptw.resp_perm(4);
// permission bit arrays // permission bit arrays
val ur_array = Reg(resetVal = Bits(0, entries)); // user read permission val ur_array = Reg(resetVal = Bits(0, entries)); // user read permission
@ -143,16 +143,16 @@ class rocketDTLB(entries: Int) extends Component
((status_s && !sr_array(tag_hit_addr).toBool) || ((status_s && !sr_array(tag_hit_addr).toBool) ||
(status_u && !ur_array(tag_hit_addr).toBool)); (status_u && !ur_array(tag_hit_addr).toBool));
io.cpu.xcpt_ld := io.cpu.xcpt_ld := access_fault_ld;
(lookup && (req_load || req_amo) && outofrange) || access_fault_ld; // (lookup && (req_load || req_amo) && outofrange) || access_fault_ld;
val access_fault_st = val access_fault_st =
tlb_hit && (req_store || req_amo) && tlb_hit && (req_store || req_amo) &&
((status_s && !sw_array(tag_hit_addr).toBool) || ((status_s && !sw_array(tag_hit_addr).toBool) ||
(status_u && !uw_array(tag_hit_addr).toBool)); (status_u && !uw_array(tag_hit_addr).toBool));
io.cpu.xcpt_st := io.cpu.xcpt_st := access_fault_st;
(lookup && (req_store || req_amo) && outofrange) || access_fault_st; // (lookup && (req_store || req_amo) && outofrange) || access_fault_st;
io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true)); io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
io.cpu.resp_busy := tlb_miss || (state != s_ready); io.cpu.resp_busy := tlb_miss || (state != s_ready);