riscv/rocket-chip
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Fix exception behavior of fmin/fmax

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This commit is contained in:
Andrew Waterman
2014-03-18 18:36:19 -07:00
parent 54cbf0c4f1
commit 5996418021
1 changed files with 5 additions and 5 deletions
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10
rocket/src/main/scala/fpu.scala
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@@ -103,10 +103,10 @@ class FPUDecoder extends Module
FSGNJ_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,Y,N,N),
FSGNJN_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,Y,N,N),
FSGNJX_D -> List(FCMD_SGNJ, N,Y,Y,Y,N,N,N,N,N,Y,N,N),
FMIN_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,Y,N,Y,Y,N,N),
FMAX_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,Y,N,Y,Y,N,N),
FMIN_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,Y,Y,N,N),
FMAX_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,Y,Y,N,N),
FMIN_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,Y,N,N,Y,N,N),
FMAX_S -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,Y,N,N,Y,N,N),
FMIN_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,Y,N,N),
FMAX_D -> List(FCMD_MINMAX, N,Y,Y,Y,N,N,N,N,N,Y,N,N),
FADD_S -> List(FCMD_ADD, N,Y,Y,Y,N,Y,Y,N,N,N,Y,Y),
FSUB_S -> List(FCMD_SUB, N,Y,Y,Y,N,Y,Y,N,N,N,Y,Y),
FMUL_S -> List(FCMD_MUL, N,Y,Y,Y,N,N,Y,N,N,N,Y,Y),
@@ -406,7 +406,7 @@ class FPU(conf: FPUConfig) extends Module
dfma.io.in.bits := req
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := ex_reg_valid && ex_ctrl.toint
fpiu.io.in.valid := ex_reg_valid && (ex_ctrl.toint || ex_ctrl.cmd === FCMD_MINMAX)
fpiu.io.in.bits := req
io.dpath.store_data := fpiu.io.out.bits.store
io.dpath.toint_data := fpiu.io.out.bits.toint