axi4: improve test harness
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5885bf29b5
@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(model.node)
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
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gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
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@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
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val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
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model.node := fuzz.node
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xbar.node := TLDelayer(0.1)(model.node)
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xbar.node := TLDelayer(0.1)(TLBuffer(TLBufferParams.flow)(TLDelayer(0.2)(model.node)))
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ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
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gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
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@ -69,7 +69,12 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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node := TLToAXI4(4)(TLDelayer(0.1)(model.node))
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node :=
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TLToAXI4(4)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.1)(
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model.node))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -84,9 +89,16 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4InputNode()
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
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val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
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ram.node := TLFragmenter(4, 16)(AXI4ToTL()(AXI4Fragmenter()(node)))
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ram.node :=
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TLFragmenter(4, 16)(
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TLDelayer(0.1)(
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TLBuffer(TLBufferParams.flow)(
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TLDelayer(0.1)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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node))))))
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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