From 583adeee88eb86169001c0b5b44c774eab91860f Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 27 Sep 2017 12:41:30 -0700 Subject: [PATCH] Separate interrupt bit from cause field in trace bundle --- src/main/scala/rocket/CSR.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 8051946b..13605307 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -155,7 +155,8 @@ class TracedInstruction(implicit p: Parameters) extends CoreBundle { val insn = UInt(width = iLen) val priv = UInt(width = 3) val exception = Bool() - val cause = UInt(width = 1 + log2Ceil(xLen)) + val interrupt = Bool() + val cause = UInt(width = log2Ceil(xLen)) val tval = UInt(width = coreMaxAddrBits max iLen) } @@ -773,7 +774,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) - t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0)) + t.cause := cause + t.interrupt := cause(xLen-1) t.tval := badaddr_value }