From 8db5bbbae0859477d6a127b2f4fde94144190cbc Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 19 Sep 2017 13:41:11 -0700 Subject: [PATCH] try to give seqmems clearer names --- src/main/scala/rocket/DCache.scala | 12 ++++++------ src/main/scala/rocket/ICache.scala | 10 +++++----- src/main/scala/rocket/NBDcache.scala | 12 ++++++------ src/main/scala/rocket/PTW.scala | 4 ++-- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 8cf787bd..3e67b194 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -35,9 +35,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (wordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits - val data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) } - val rdata = for ((array, i) <- data_arrays zipWithIndex) yield { - val valid = io.req.valid && (Bool(data_arrays.size == 1) || io.req.bits.wordMask(i)) + val dcache_data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) } + val rdata = for ((array, i) <- dcache_data_arrays zipWithIndex) yield { + val valid = io.req.valid && (Bool(dcache_data_arrays.size == 1) || io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wData = wWords(i).grouped(encBits) array.write(addr, Vec((0 until nWays).flatMap(i => wData)), wMask) @@ -72,7 +72,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // tags val replacer = cacheParams.replacement val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8)) - val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth)))) + val dcache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth)))) // data val data = Module(new DCacheDataArray) @@ -182,9 +182,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { when (metaReq.valid && metaReq.bits.write) { val wdata = tECC.encode(metaReq.bits.data.asUInt) val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.toBools - tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask) + dcache_tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask) } - val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) + val s1_meta = dcache_tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> untagBits val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 330a7133..a0e2d5e2 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -168,13 +168,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) v } - val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits)))) - val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid) + val icache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits)))) + val tag_rdata = icache_tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid) val accruedRefillError = Reg(Bool()) val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError) when (refill_done) { val enc_tag = tECC.encode(Cat(refillError, refill_tag)) - tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _)) + icache_tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _)) } val vb_array = Reg(init=Bits(0, nSets*nWays)) @@ -216,8 +216,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1) require(tl_out.d.bits.data.getWidth % wordBits == 0) - val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) } - for ((data_array, i) <- data_arrays zipWithIndex) { + val icache_data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) } + for ((data_array, i) <- icache_data_arrays zipWithIndex) { def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles)) val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr)) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index 8d9899d4..9cf462c3 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -628,12 +628,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val resp = Wire(Vec(rowWords, Bits(width = encRowBits))) val r_raddr = RegEnable(io.read.bits.addr, io.read.valid) for (i <- 0 until resp.size) { - val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) + val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) { val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)) - array.write(waddr, data, wway_en.toBools) + nbdcache_data_array.write(waddr, data, wway_en.toBools) } - resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt + resp(i) := nbdcache_data_array.read(raddr, rway_en.orR && io.read.valid).asUInt } for (dw <- 0 until rowWords) { val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw))) @@ -645,12 +645,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { } } else { for (w <- 0 until nWays) { - val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) + val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits))) when (io.write.bits.way_en(w) && io.write.valid) { val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i)) - array.write(waddr, data, io.write.bits.wmask.toBools) + nbdcache_data_array.write(waddr, data, io.write.bits.wmask.toBools) } - io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt + io.resp(w) := nbdcache_data_array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt } } diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 768c3167..0f77fb32 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -135,7 +135,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( val l2_refill = RegNext(false.B) io.dpath.perf.l2miss := false - val (l2_hit, l2_valid, l2_pte) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, Wire(new PTE)) else { + val (l2_hit, l2_valid, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, Wire(new PTE), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) val idxBits = log2Ceil(coreParams.nL2TLBEntries) @@ -191,7 +191,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( s2_pte.g := s2_g s2_pte.v := true - (s2_hit, s2_valid && s2_valid_bit, s2_pte) + (s2_hit, s2_valid && s2_valid_bit, s2_pte, Some(ram)) } io.mem.req.valid := state === s_req && !l2_valid