riscv/rocket-chip
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re-generalize scoreboard

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This commit is contained in:
Andrew Waterman 2013-01-24 18:00:39 -08:00
parent 1fbc20450e
commit 575bd3445a
1 changed files with 4 additions and 7 deletions
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11
rocket/src/main/scala/ctrl.scala
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@ -601,12 +601,9 @@ class Control(implicit conf: RocketConfiguration) extends Component
val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || vec_replay || io.dpath.pcr_replay val replay_wb = io.dmem.resp.bits.nack || wb_reg_replay || vec_replay || io.dpath.pcr_replay
class Scoreboard class Scoreboard(n: Int)
{ {
// val r = Reg(resetVal = Bits(0)) val r = Reg(resetVal = Bits(0, n))
// RIMAS: explicitly set width to 32, otherwise Chisel would set it to 1024
// and cause a ton of warnings during synthesis
val r = Reg(resetVal = Bits(0,32))
var next = r var next = r
var ens = Bool(false) var ens = Bool(false)
def apply(addr: UFix) = r(addr) def apply(addr: UFix) = r(addr)
@ -620,12 +617,12 @@ class Control(implicit conf: RocketConfiguration) extends Component
} }
} }
val sboard = new Scoreboard val sboard = new Scoreboard(32)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr) sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr) sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
val id_stall_fpu = if (conf.fpu) { val id_stall_fpu = if (conf.fpu) {
val fp_sboard = new Scoreboard val fp_sboard = new Scoreboard(32)
fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr) fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr)
fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)