From 5725e17969247196dd4d0356a538c75b922415de Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 23 Feb 2018 12:50:51 -0800 Subject: [PATCH] subsystem: even more general coupler methods --- src/main/scala/subsystem/FrontBus.scala | 11 +-- src/main/scala/subsystem/PeripheryBus.scala | 102 ++++++++------------ src/main/scala/subsystem/SystemBus.scala | 30 ++---- src/main/scala/tilelink/BusWrapper.scala | 4 +- 4 files changed, 55 insertions(+), 92 deletions(-) diff --git a/src/main/scala/subsystem/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala index 65d27bf5..0800493e 100644 --- a/src/main/scala/subsystem/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -21,21 +21,18 @@ class FrontBus(params: FrontBusParams, val crossing: SubsystemClockCrossing = Sy (name: Option[String] = None, buffers: Int = 1) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { - from("port" named name) { - val nodes = TLFIFOFixer(TLFIFOFixer.all) +: TLBuffer.chain(buffers) - inwardNode :=* nodes.reduce(_ :=* _) :=* gen - } + from("port" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } } - def fromMasterNode( name: Option[String] = None, buffers: Int = 1)(gen: TLOutwardNode) { - from("master" named name) { bufferFrom(buffers) :=* gen } + def fromMasterNode(name: Option[String] = None, buffers: Int = 1)(gen: TLOutwardNode) { + from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } } def fromMaster[D,U,E,B <: Data] (name: Option[String] = None, buffers: Int = 1) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { - from("master" named name) { bufferFrom(buffers) :=* gen } + from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } } def fromCoherentChip(gen: => TLNode): TLInwardNode = { diff --git a/src/main/scala/subsystem/PeripheryBus.scala b/src/main/scala/subsystem/PeripheryBus.scala index c2d7c569..a1c42883 100644 --- a/src/main/scala/subsystem/PeripheryBus.scala +++ b/src/main/scala/subsystem/PeripheryBus.scala @@ -21,94 +21,73 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross with HasTLXbarPhy with HasCrossing { - def toSlave[D,U,E,B <: Data]( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => NodeHandle[ - TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, - D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { + def toSlave[D,U,E,B <: Data] + (name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { to("slave" named name) { gen :*= bufferTo(buffer) } } - def toVariableWidthSlaveNode( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: TLInwardNode) { - to("slave" named name) { - gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer) - } + def toVariableWidthSlaveNode(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(node: TLInwardNode) { toVariableWidthSlaveNodeOption(name, buffer)(Some(node)) } + + def toVariableWidthSlaveNodeOption(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(node: Option[TLInwardNode]) { + node foreach { n => to("slave" named name) { n :*= fragmentTo(buffer) } } } - def toVariableWidthSlave[D,U,E,B <: Data]( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => NodeHandle[ - TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, - D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { - to("slave" named name) { - gen :*= fragmentTo(params.beatBytes, params.blockBytes, buffer) - } + def toVariableWidthSlave[D,U,E,B <: Data] + (name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { + to("slave" named name) { gen :*= fragmentTo(buffer) } } - def toFixedWidthSlaveNode( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: TLInwardNode) { + def toFixedWidthSlaveNode(name: Option[String] = None, buffer: BufferParams = BufferParams.none)(gen: TLInwardNode) { to("slave" named name) { gen :*= fixedWidthTo(buffer) } } - def toFixedWidthSlave[D,U,E,B <: Data]( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => NodeHandle[ - TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, - D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { + def toFixedWidthSlave[D,U,E,B <: Data] + (name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { to("slave" named name) { gen :*= fixedWidthTo(buffer) } } - def toFixedWidthSingleBeatSlaveNode( - widthBytes: Int, - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) + def toFixedWidthSingleBeatSlaveNode + (widthBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none) (gen: TLInwardNode) { to("slave" named name) { gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer) } } - def toFixedWidthSingleBeatSlave[D,U,E,B <: Data]( - widthBytes: Int, - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => NodeHandle[ - TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle, - D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { + def toFixedWidthSingleBeatSlave[D,U,E,B <: Data] + (widthBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { to("slave" named name) { gen :*= TLFragmenter(widthBytes, params.blockBytes) :*= fixedWidthTo(buffer) } } - def toLargeBurstSlave( - maxXferBytes: Int, - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => TLNode): TLOutwardNode = { + def toLargeBurstSlave[D,U,E,B <: Data] + (maxXferBytes: Int, name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { to("slave" named name) { gen :*= fragmentTo(params.beatBytes, maxXferBytes, buffer) } } - def toFixedWidthPort[D,U,E,B <: Data]( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = { + def toFixedWidthPort[D,U,E,B <: Data] + (name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = + TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { to("port" named name) { gen := fixedWidthTo(buffer) } } - def fromSystemBus( - arithmetic: Boolean = true, - buffer: BufferParams = BufferParams.default) + def fromSystemBus + (arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default) (gen: => TLOutwardNode) { from("sbus") { (inwardNode @@ -118,17 +97,16 @@ class PeripheryBus(params: PeripheryBusParams, val crossing: SubsystemClockCross } } - def fromOtherMaster( - name: Option[String] = None, - buffer: BufferParams = BufferParams.none) - (gen: => TLNode): TLInwardNode = { + def fromOtherMaster[D,U,E,B <: Data] + (name: Option[String] = None, buffer: BufferParams = BufferParams.none) + (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = + TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { from("master" named name) { bufferFrom(buffer) :=* gen } } - def toTile( - name: Option[String] = None, - buffers: Int = 0) + def toTile + (name: Option[String] = None, buffers: Int = 0) (gen: => TLNode): TLOutwardNode = { to("tile" named name) { FlipRendering { implicit p => gen :*= bufferTo(buffers) diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala index b9327a86..320f1a69 100644 --- a/src/main/scala/subsystem/SystemBus.scala +++ b/src/main/scala/subsystem/SystemBus.scala @@ -18,6 +18,9 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr private val master_splitter = LazyModule(new TLSplitter) inwardNode :=* master_splitter.node + protected def fixFromThenSplit(policy: TLFIFOFixer.Policy, buffers: Int): TLInwardNode = + master_splitter.node :=* TLBuffer.chain(buffers).foldLeft(TLFIFOFixer(policy))(_ :=* _) + def busView = master_splitter.node.edges.in.head def toPeripheryBus(buffer: BufferParams = BufferParams.none) @@ -59,9 +62,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr (name: Option[String] = None, buffer: BufferParams = BufferParams.default) (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B] = TLIdentity.gen): OutwardNodeHandle[D,U,E,B] = { - to("slave" named name) { - gen :*= TLFragmenter(params.beatBytes, params.blockBytes) :*= bufferTo(buffer) - } + to("slave" named name) { gen :*= fragmentTo(buffer) } } def fromFrontBus(gen: => TLNode): TLInwardNode = { @@ -72,8 +73,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr (name: Option[String], buffers: Int = 0, cork: Option[Boolean] = None) (gen: => TLNode): TLInwardNode = { from("tile" named name) { - (List(master_splitter.node, TLFIFOFixer(TLFIFOFixer.allUncacheable)) ++ TLBuffer.chain(buffers)) - .reduce(_ :=* _) :=* gen + fixFromThenSplit(TLFIFOFixer.allUncacheable, buffers) :=* gen } } @@ -88,34 +88,20 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr (name: Option[String] = None, buffers: Int = 0) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { - from("port" named name) { - (List( - master_splitter.node, - TLFIFOFixer(TLFIFOFixer.all)) ++ - TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen - } + from("port" named name) { fixFromThenSplit(TLFIFOFixer.all, buffers) :=* gen } } def fromCoherentMaster[D,U,E,B <: Data] (name: Option[String] = None, buffers: Int = 0) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { - from("coherent_master" named name) { - (inwardNode - :=* TLBuffer.chain(buffers).foldLeft(TLFIFOFixer(TLFIFOFixer.all))(_ :=* _) - :=* gen) - } + from("coherent_master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } } def fromMaster[D,U,E,B <: Data] (name: Option[String] = None, buffers: Int = 0) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { - from("master" named name) { - (master_splitter.node - :=* TLFIFOFixer(TLFIFOFixer.all) - :=* TLBuffer.chain(buffers).reduce(_ :=* _) - :=* gen) - } + from("master" named name) { fixFromThenSplit(TLFIFOFixer.all, buffers) :=* gen } } } diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala index 2e10a73a..ecb784ae 100644 --- a/src/main/scala/tilelink/BusWrapper.scala +++ b/src/main/scala/tilelink/BusWrapper.scala @@ -35,6 +35,9 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici protected def bufferFrom(buffers: Int): TLInwardNode = TLBuffer.chain(buffers).foldLeft(inwardNode)(_ :=* _) + protected def fixFrom(policy: TLFIFOFixer.Policy, buffers: Int): TLInwardNode = + inwardNode :=* TLBuffer.chain(buffers).foldLeft(TLFIFOFixer(policy))(_ :=* _) + protected def bufferTo(buffer: BufferParams): TLOutwardNode = TLBuffer(buffer) :*= delayNode :*= outwardNode @@ -50,7 +53,6 @@ abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implici protected def fragmentTo(minSize: Int, maxSize: Int, buffer: BufferParams): TLOutwardNode = TLFragmenter(minSize, maxSize) :*= bufferTo(buffer) - protected def delayNode(implicit p: Parameters): TLNode = { val delayProb = p(TLBusDelayProbability) if (delayProb > 0.0) {