Implement NASTI-based Mem/IO interconnect
This commit is contained in:
Howard Mao
parent
c6bcc832a1
commit
56ecdff52d
2
chisel
2
chisel
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Subproject commit 1f01401e9b4b0136303e5ae75a1196aaa222d80f
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Subproject commit 179f5c6a6fd8b9f0195073ed204ddc07b1a50363
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@ -1 +1 @@
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Subproject commit 1136e89f0f4037c31e48aad4b13260ff17039811
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Subproject commit 83b76aa258dccdf4b7b9f3d4c7756549ed37be9d
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@ -1 +1 @@
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Subproject commit f98a4d64e7fa2e19968f8275be94efc8415d20a4
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Subproject commit 3ad77802d200be7e1506a9add0faef3acf30bcd1
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2
rocket
2
rocket
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Subproject commit caa109c376a3c5fd12aea9d976c140982d9cfd8c
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Subproject commit 7a520740dc4c41694491e6628ff6233b4c76acd8
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@ -35,15 +35,13 @@ class DefaultConfig extends ChiselConfig (
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case MIFTagBits => Dump("MEM_TAG_BITS",
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log2Up(site(NAcquireTransactors)+2) +
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log2Up(site(NBanksPerMemoryChannel)) +
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log2Up(site(NMemoryChannels)) + /* TODO: Remove for multichannel Top */
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1)
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log2Up(site(NMemoryChannels)))
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case MIFDataBits => Dump("MEM_DATA_BITS", 128)
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case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
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case NASTIDataBits => site(MIFDataBits)
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case NASTIAddrBits => site(MIFAddrBits)
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case NASTIAddrBits => site(PAddrBits)
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case NASTIIdBits => site(MIFTagBits)
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case UseNASTI => false
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//Params used by all caches
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case NSets => findBy(CacheName)
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case NWays => findBy(CacheName)
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@ -72,6 +70,7 @@ class DefaultConfig extends ChiselConfig (
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case StoreDataQueueDepth => 17
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case ReplayQueueDepth => 16
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case NMSHRs => Knob("L1D_MSHRS")
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case NIOMSHRs => 1
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case LRSCCycles => 32
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//L2 Memory System Params
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case NAcquireTransactors => 7
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@ -119,6 +118,7 @@ class DefaultConfig extends ChiselConfig (
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case TLNClients => site(TLNCachingClients) + site(TLNCachelessClients)
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case TLDataBits => site(CacheBlockBytes)*8/site(TLDataBeats)
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case TLDataBeats => 4
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case TLWriteMaskBits => (site(TLDataBits) - 1) / 8 + 1
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case TLNetworkIsOrderedP2P => false
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case TLNManagers => findBy(TLId)
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case TLNCachingClients => findBy(TLId)
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@ -133,7 +133,7 @@ class DefaultConfig extends ChiselConfig (
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case TLNCachelessClients => site(NTiles) + 1
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case TLCoherencePolicy => new MESICoherence(site(L2DirectoryRepresentation))
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case TLMaxManagerXacts => site(NAcquireTransactors) + 2
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case TLMaxClientXacts => max(site(NMSHRs),
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case TLMaxClientXacts => max(site(NMSHRs) + site(NIOMSHRs),
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if(site(BuildRoCC).isEmpty) 1
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else site(RoCCMaxTaggedMemXacts))
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case TLMaxClientsPerPort => if(site(BuildRoCC).isEmpty) 1 else 3
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@ -155,6 +155,18 @@ class DefaultConfig extends ChiselConfig (
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case CacheBlockBytes => 64
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case UseBackupMemoryPort => true
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case MMIOBase => BigInt(1 << 30) // 1 GB
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case ExternalIOStart => 2 * site(MMIOBase)
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case NASTIAddrMap => Seq(
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("mem", None, MemSize(site(MMIOBase), AddrMap.RWX)),
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("conf", None, Submap(site(ExternalIOStart) - site(MMIOBase),
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("csr0", None, MemSize(1 << 15, AddrMap.RW)),
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("scr", None, MemSize(site(HTIFNSCR) * 8, AddrMap.RW)))),
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("io", Some(site(ExternalIOStart)),
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MemSize(2 * site(MMIOBase), AddrMap.RW)))
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case NASTIAddrHashMap => new AddrHashMap(site(NASTIAddrMap))
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case NASTINMasters => site(TLNManagers) + 1
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case NASTINSlaves => site(NASTIAddrHashMap).nEntries
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}},
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knobValues = {
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case "NTILES" => 1
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@ -254,3 +266,7 @@ class SmallConfig extends ChiselConfig (
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class DefaultFPGASmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultFPGAConfig)
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class ExampleSmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultConfig)
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class MultibankConfig extends ChiselConfig(new With2Banks ++ new DefaultConfig)
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class MultibankL2Config extends ChiselConfig(
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new With2Banks ++ new WithL2Cache ++ new DefaultConfig)
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@ -26,8 +26,8 @@ case object UseBackupMemoryPort extends Field[Boolean]
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case object BuildL2CoherenceManager extends Field[() => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool) => Tile]]
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/** Which protocol to use to talk to memory/devices */
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case object UseNASTI extends Field[Boolean]
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/** Start address of the "io" region in the memory map */
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case object ExternalIOStart extends Field[BigInt]
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/** Utility trait for quick access to some relevant parameters */
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trait TopLevelParameters extends UsesParameters {
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@ -40,6 +40,7 @@ trait TopLevelParameters extends UsesParameters {
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val nMemReqs = params(NOutstandingMemReqsPerChannel)
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val mifAddrBits = params(MIFAddrBits)
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val mifDataBeats = params(MIFDataBeats)
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val scrAddrBits = log2Up(params(HTIFNSCR))
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require(lsb + log2Up(nBanks) < mifAddrBits)
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}
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@ -61,7 +62,8 @@ class TopIO extends BasicTopIO {
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}
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class MultiChannelTopIO extends BasicTopIO with TopLevelParameters {
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val mem = Vec(new MemIO, nMemChannels)
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val mem = Vec(new NASTIMasterIO, nMemChannels)
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val mmio = new NASTIMasterIO
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}
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/** Top-level module for the chip */
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@ -70,11 +72,19 @@ class Top extends Module with TopLevelParameters {
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val io = new TopIO
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if(!params(UseZscale)) {
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val temp = Module(new MultiChannelTop)
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val arb = Module(new MemIOArbiter(nMemChannels))
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arb.io.inner <> temp.io.mem
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io.mem <> arb.io.outer
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val arb = Module(new NASTIArbiter(nMemChannels))
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val conv = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
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arb.io.master <> temp.io.mem
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conv.io.nasti <> arb.io.slave
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io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
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io.mem.req_data <> Queue(conv.io.mem.req_data, mifDataBeats)
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conv.io.mem.resp <> Queue(io.mem.resp, mifDataBeats)
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io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
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io.host <> temp.io.host
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// tie off the mmio port
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val errslave = Module(new NASTIErrorSlave)
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errslave.io <> temp.io.mmio
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} else {
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val temp = Module(new ZscaleTop)
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io.host <> temp.io.host
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@ -93,8 +103,8 @@ class MultiChannelTop extends Module with TopLevelParameters {
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case ((hl, tile), i) =>
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tile.io.host.id := UInt(i)
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.pcr_req <> Queue(hl.pcr_req)
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hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
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tile.io.host.pcr.req <> Queue(hl.pcr.req)
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hl.pcr.resp <> Queue(tile.io.host.pcr.resp)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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hl.debug_stats_pcr := tile.io.host.debug_stats_pcr
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@ -105,6 +115,7 @@ class MultiChannelTop extends Module with TopLevelParameters {
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uncore.io.tiles_uncached <> tileList.map(_.io.uncached)
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io.host <> uncore.io.host
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io.mem <> uncore.io.mem
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io.mmio <> uncore.io.mmio
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if(params(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
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}
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@ -116,11 +127,12 @@ class MultiChannelTop extends Module with TopLevelParameters {
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class Uncore extends Module with TopLevelParameters {
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val io = new Bundle {
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val host = new HostIO
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val mem = Vec(new MemIO, nMemChannels)
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val mem = Vec(new NASTIMasterIO, nMemChannels)
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val tiles_cached = Vec(new ClientTileLinkIO, nTiles).flip
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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val htif = Vec(new HTIFIO, nTiles).flip
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val mem_backup_ctrl = new MemBackupCtrlIO
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val mmio = new NASTIMasterIO
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}
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val htif = Module(new HTIF(CSRs.mreset)) // One HTIF module per chip
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@ -130,13 +142,36 @@ class Uncore extends Module with TopLevelParameters {
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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for (i <- 0 until nTiles) {
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io.htif(i).reset := htif.io.cpu(i).reset
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io.htif(i).id := htif.io.cpu(i).id
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htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
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io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
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htif.io.cpu(i).debug_stats_pcr <> io.htif(i).debug_stats_pcr
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val pcr_arb = Module(new SMIArbiter(2, 64, 12))
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pcr_arb.io.in(0) <> htif.io.cpu(i).pcr
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pcr_arb.io.in(1) <> outmemsys.io.pcr(i)
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io.htif(i).pcr <> pcr_arb.io.out
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}
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// Arbitrate SCR access between MMIO and HTIF
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val scrArb = Module(new SMIArbiter(2, 64, scrAddrBits))
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val scrFile = Module(new SCRFile)
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scrArb.io.in(0) <> htif.io.scr
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scrArb.io.in(1) <> outmemsys.io.scr
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scrFile.io.smi <> scrArb.io.out
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// scrFile.io.scr <> (... your SCR connections ...)
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// Wire the htif to the memory port(s) and host interface
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io.host.debug_stats_pcr := htif.io.host.debug_stats_pcr
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htif.io.cpu <> io.htif
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io.mem <> outmemsys.io.mem
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io.mmio <> outmemsys.io.mmio
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if(params(UseBackupMemoryPort)) {
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outmemsys.io.mem_backup_en := io.mem_backup_ctrl.en
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VLSIUtils.padOutHTIFWithDividedClock(htif.io, outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr,
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outmemsys.io.mem_backup, io.mem_backup_ctrl, io.host, htifW)
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} else {
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htif.io.host.out <> io.host.out
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htif.io.host.in <> io.host.in
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@ -152,9 +187,12 @@ class OuterMemorySystem extends Module with TopLevelParameters {
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val tiles_uncached = Vec(new ClientUncachedTileLinkIO, nTiles).flip
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(Bool(), nTiles).asInput
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val mem = Vec(new MemIO, nMemChannels)
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val mem = Vec(new NASTIMasterIO, nMemChannels)
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val mem_backup = new MemSerializedIO(htifW)
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val mem_backup_en = Bool(INPUT)
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val pcr = Vec(new SMIIO(64, 12), nTiles)
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val scr = new SMIIO(64, scrAddrBits)
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val mmio = new NASTIMasterIO
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}
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// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
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@ -170,43 +208,59 @@ class OuterMemorySystem extends Module with TopLevelParameters {
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else new RocketChipTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering, postBuffering))
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// Create point(s) of coherence serialization
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val managerEndpoints = List.fill(nMemChannels) {
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List.fill(nBanksPerMemChannel) {
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params(BuildL2CoherenceManager)()}}
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managerEndpoints.flatten.foreach { _.incoherent := io.incoherent }
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val nManagers = nMemChannels * nBanksPerMemChannel
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val managerEndpoints = List.fill(nManagers) { params(BuildL2CoherenceManager)()}
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managerEndpoints.foreach { _.incoherent := io.incoherent }
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// Wire the tiles and htif to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients <> ordered_clients
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l1tol2net.io.managers <> managerEndpoints.flatMap(_.map(_.innerTL))
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL)
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// Create a converter between TileLinkIO and MemIO for each channel
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val outerTLParams = params.alterPartial({ case TLId => "L2ToMC" })
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val backendBuffering = TileLinkDepths(0,0,0,0,0)
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val mem_channels = managerEndpoints.map { banks =>
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if(!params(UseNASTI)) {
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val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
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val conv = Module(new MemPipeIOTileLinkIOConverter(nMemReqs))(outerTLParams)
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arb.io.clients <> banks.map(_.outerTL)
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arb.io.managers.head <> conv.io.tl
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MemIOMemPipeIOConverter(conv.io.mem)
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} else {
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val arb = Module(new RocketChipTileLinkArbiter(managerDepths = backendBuffering))(outerTLParams)
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val conv1 = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams)
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val conv2 = Module(new MemIONASTISlaveIOConverter(params(CacheBlockOffsetBits)))
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val conv3 = Module(new MemPipeIOMemIOConverter(nMemReqs))
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arb.io.clients <> banks.map(_.outerTL)
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arb.io.managers.head <> conv1.io.tl
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conv2.io.nasti <> conv1.io.nasti
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conv3.io.cpu.req_cmd <> Queue(conv2.io.mem.req_cmd, 2)
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conv3.io.cpu.req_data <> Queue(conv2.io.mem.req_data, mifDataBeats)
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conv2.io.mem.resp <> conv3.io.cpu.resp
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MemIOMemPipeIOConverter(conv3.io.mem)
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val addrMap = params(NASTIAddrHashMap)
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println("Generated Address Map")
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for ((name, base, size, _) <- addrMap.sortedEntries) {
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println(f"\t$name%s $base%x - ${base + size - 1}%x")
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}
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val interconnect = Module(new NASTITopInterconnect)
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for ((bank, i) <- managerEndpoints.zipWithIndex) {
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val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
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val conv = Module(new NASTIMasterIOTileLinkIOConverter)(outerTLParams)
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unwrap.io.in <> bank.outerTL
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conv.io.tl <> unwrap.io.out
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interconnect.io.masters(i) <> conv.io.nasti
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}
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val rtc = Module(new RTC(CSRs.mtime))
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interconnect.io.masters(nManagers) <> rtc.io
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for (i <- 0 until nTiles) {
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val csrName = s"conf:csr$i"
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val csrPort = addrMap(csrName).port
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val conv = Module(new SMIIONASTISlaveIOConverter(64, 12))
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conv.io.nasti <> interconnect.io.slaves(csrPort)
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io.pcr(i) <> conv.io.smi
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}
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val conv = Module(new SMIIONASTISlaveIOConverter(64, scrAddrBits))
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conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
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io.scr <> conv.io.smi
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io.mmio <> interconnect.io.slaves(addrMap("io").port)
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val mem_channels = interconnect.io.slaves.take(nMemChannels)
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// Create a SerDes for backup memory port
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if(params(UseBackupMemoryPort)) {
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VLSIUtils.doOuterMemorySystemSerdes(mem_channels, io.mem, io.mem_backup, io.mem_backup_en, nMemChannels, params(HTIFWidth))
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VLSIUtils.doOuterMemorySystemSerdes(
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mem_channels, io.mem, io.mem_backup, io.mem_backup_en,
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nMemChannels, params(HTIFWidth), params(CacheBlockOffsetBits))
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} else { io.mem <> mem_channels }
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}
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@ -15,52 +15,69 @@ class MemDessert extends Module {
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object VLSIUtils {
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def doOuterMemorySystemSerdes(
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llcs: Seq[MemIO],
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mems: Seq[MemIO],
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llcs: Seq[NASTIMasterIO],
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mems: Seq[NASTIMasterIO],
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backup: MemSerializedIO,
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en: Bool,
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nMemChannels: Int,
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htifWidth: Int) {
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val arb = Module(new MemIOArbiter(nMemChannels))
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htifWidth: Int,
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blockOffsetBits: Int) {
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val arb = Module(new NASTIArbiter(nMemChannels))
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val conv = Module(new MemIONASTISlaveIOConverter(blockOffsetBits))
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val mem_serdes = Module(new MemSerdes(htifWidth))
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mem_serdes.io.wide <> arb.io.outer
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conv.io.nasti <> arb.io.slave
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mem_serdes.io.wide <> conv.io.mem
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backup <> mem_serdes.io.narrow
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llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
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llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
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mem.req_cmd.valid := llc.req_cmd.valid && !en
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mem.req_cmd.bits := llc.req_cmd.bits
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wide.req_cmd.valid := llc.req_cmd.valid && en
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wide.req_cmd.bits := llc.req_cmd.bits
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llcs zip mems zip arb.io.master foreach { case ((llc, mem), wide) =>
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llc.ar.ready := Mux(en, wide.ar.ready, mem.ar.ready)
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mem.ar.valid := llc.ar.valid && !en
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mem.ar.bits := llc.ar.bits
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wide.ar.valid := llc.ar.valid && en
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wide.ar.bits := llc.ar.bits
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llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
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mem.req_data.valid := llc.req_data.valid && !en
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mem.req_data.bits := llc.req_data.bits
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wide.req_data.valid := llc.req_data.valid && en
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wide.req_data.bits := llc.req_data.bits
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llc.aw.ready := Mux(en, wide.aw.ready, mem.aw.ready)
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mem.aw.valid := llc.aw.valid && !en
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mem.aw.bits := llc.aw.bits
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wide.aw.valid := llc.aw.valid && en
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wide.aw.bits := llc.aw.bits
|
||||
|
||||
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
|
||||
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
|
||||
mem.resp.ready := llc.resp.ready && !en
|
||||
wide.resp.ready := llc.resp.ready && en
|
||||
llc.w.ready := Mux(en, wide.w.ready, mem.w.ready)
|
||||
mem.w.valid := llc.w.valid && !en
|
||||
mem.w.bits := llc.w.bits
|
||||
wide.w.valid := llc.w.valid && en
|
||||
wide.w.bits := llc.w.bits
|
||||
|
||||
llc.b.valid := Mux(en, wide.b.valid, mem.b.valid)
|
||||
llc.b.bits := Mux(en, wide.b.bits, mem.b.bits)
|
||||
mem.b.ready := llc.b.ready && !en
|
||||
wide.b.ready := llc.b.ready && en
|
||||
|
||||
llc.r.valid := Mux(en, wide.r.valid, mem.r.valid)
|
||||
llc.r.bits := Mux(en, wide.r.bits, mem.r.bits)
|
||||
mem.r.ready := llc.r.ready && !en
|
||||
wide.r.ready := llc.r.ready && en
|
||||
}
|
||||
}
|
||||
|
||||
def padOutHTIFWithDividedClock(
|
||||
htif: HTIFModuleIO,
|
||||
htif: HostIO,
|
||||
scr: SCRIO,
|
||||
child: MemSerializedIO,
|
||||
parent: MemBackupCtrlIO,
|
||||
host: HostIO,
|
||||
htifW: Int) {
|
||||
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
|
||||
hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
|
||||
hio.io.set_divisor.bits := htif.scr.wdata
|
||||
htif.scr.rdata(63) := hio.io.divisor
|
||||
hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
|
||||
hio.io.set_divisor.bits := scr.wdata
|
||||
scr.rdata(63) := hio.io.divisor
|
||||
|
||||
hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
|
||||
hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
|
||||
htif.host.out.ready := hio.io.out_fast.ready
|
||||
child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
|
||||
hio.io.out_fast.valid := htif.out.valid || child.req.valid
|
||||
hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
|
||||
htif.out.ready := hio.io.out_fast.ready
|
||||
child.req.ready := hio.io.out_fast.ready && !htif.out.valid
|
||||
host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
|
||||
host.out.bits := hio.io.out_slow.bits
|
||||
parent.out_valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
|
||||
@ -72,9 +89,9 @@ object VLSIUtils {
|
||||
host.in.ready := hio.io.in_slow.ready
|
||||
child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
|
||||
child.resp.bits := hio.io.in_fast.bits
|
||||
htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
|
||||
htif.host.in.bits := hio.io.in_fast.bits
|
||||
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
|
||||
htif.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
|
||||
htif.in.bits := hio.io.in_fast.bits
|
||||
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.in.ready)
|
||||
host.clk := hio.io.clk_slow
|
||||
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
|
||||
}
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit 5b76a91b2ed22ab203730d32202fa653431cf17c
|
||||
Subproject commit d6895713cf4c0fcc53a3507f0c376716be8b0dce
|
||||
Loading…
Reference in New Issue
Block a user