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Implement NASTI-based Mem/IO interconnect

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This commit is contained in:
Howard Mao
2015-08-06 12:51:18 -07:00
parent c6bcc832a1
commit 56ecdff52d
8 changed files with 166 additions and 79 deletions
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79
src/main/scala/Vlsi.scala
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@ -15,52 +15,69 @@ class MemDessert extends Module {
object VLSIUtils {
def doOuterMemorySystemSerdes(
llcs: Seq[MemIO],
mems: Seq[MemIO],
llcs: Seq[NASTIMasterIO],
mems: Seq[NASTIMasterIO],
backup: MemSerializedIO,
en: Bool,
nMemChannels: Int,
htifWidth: Int) {
val arb = Module(new MemIOArbiter(nMemChannels))
htifWidth: Int,
blockOffsetBits: Int) {
val arb = Module(new NASTIArbiter(nMemChannels))
val conv = Module(new MemIONASTISlaveIOConverter(blockOffsetBits))
val mem_serdes = Module(new MemSerdes(htifWidth))
mem_serdes.io.wide <> arb.io.outer
conv.io.nasti <> arb.io.slave
mem_serdes.io.wide <> conv.io.mem
backup <> mem_serdes.io.narrow
llcs zip mems zip arb.io.inner foreach { case ((llc, mem), wide) =>
llc.req_cmd.ready := Mux(en, wide.req_cmd.ready, mem.req_cmd.ready)
mem.req_cmd.valid := llc.req_cmd.valid && !en
mem.req_cmd.bits := llc.req_cmd.bits
wide.req_cmd.valid := llc.req_cmd.valid && en
wide.req_cmd.bits := llc.req_cmd.bits
llcs zip mems zip arb.io.master foreach { case ((llc, mem), wide) =>
llc.ar.ready := Mux(en, wide.ar.ready, mem.ar.ready)
mem.ar.valid := llc.ar.valid && !en
mem.ar.bits := llc.ar.bits
wide.ar.valid := llc.ar.valid && en
wide.ar.bits := llc.ar.bits
llc.req_data.ready := Mux(en, wide.req_data.ready, mem.req_data.ready)
mem.req_data.valid := llc.req_data.valid && !en
mem.req_data.bits := llc.req_data.bits
wide.req_data.valid := llc.req_data.valid && en
wide.req_data.bits := llc.req_data.bits
llc.aw.ready := Mux(en, wide.aw.ready, mem.aw.ready)
mem.aw.valid := llc.aw.valid && !en
mem.aw.bits := llc.aw.bits
wide.aw.valid := llc.aw.valid && en
wide.aw.bits := llc.aw.bits
llc.resp.valid := Mux(en, wide.resp.valid, mem.resp.valid)
llc.resp.bits := Mux(en, wide.resp.bits, mem.resp.bits)
mem.resp.ready := llc.resp.ready && !en
wide.resp.ready := llc.resp.ready && en
llc.w.ready := Mux(en, wide.w.ready, mem.w.ready)
mem.w.valid := llc.w.valid && !en
mem.w.bits := llc.w.bits
wide.w.valid := llc.w.valid && en
wide.w.bits := llc.w.bits
llc.b.valid := Mux(en, wide.b.valid, mem.b.valid)
llc.b.bits := Mux(en, wide.b.bits, mem.b.bits)
mem.b.ready := llc.b.ready && !en
wide.b.ready := llc.b.ready && en
llc.r.valid := Mux(en, wide.r.valid, mem.r.valid)
llc.r.bits := Mux(en, wide.r.bits, mem.r.bits)
mem.r.ready := llc.r.ready && !en
wide.r.ready := llc.r.ready && en
}
}
def padOutHTIFWithDividedClock(
htif: HTIFModuleIO,
htif: HostIO,
scr: SCRIO,
child: MemSerializedIO,
parent: MemBackupCtrlIO,
host: HostIO,
htifW: Int) {
val hio = Module((new SlowIO(512)) { Bits(width = htifW+1) })
hio.io.set_divisor.valid := htif.scr.wen && (htif.scr.waddr === UInt(63))
hio.io.set_divisor.bits := htif.scr.wdata
htif.scr.rdata(63) := hio.io.divisor
hio.io.set_divisor.valid := scr.wen && (scr.waddr === UInt(63))
hio.io.set_divisor.bits := scr.wdata
scr.rdata(63) := hio.io.divisor
hio.io.out_fast.valid := htif.host.out.valid || child.req.valid
hio.io.out_fast.bits := Cat(htif.host.out.valid, Mux(htif.host.out.valid, htif.host.out.bits, child.req.bits))
htif.host.out.ready := hio.io.out_fast.ready
child.req.ready := hio.io.out_fast.ready && !htif.host.out.valid
hio.io.out_fast.valid := htif.out.valid || child.req.valid
hio.io.out_fast.bits := Cat(htif.out.valid, Mux(htif.out.valid, htif.out.bits, child.req.bits))
htif.out.ready := hio.io.out_fast.ready
child.req.ready := hio.io.out_fast.ready && !htif.out.valid
host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htifW)
host.out.bits := hio.io.out_slow.bits
parent.out_valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htifW)
@ -72,9 +89,9 @@ object VLSIUtils {
host.in.ready := hio.io.in_slow.ready
child.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htifW)
child.resp.bits := hio.io.in_fast.bits
htif.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
htif.host.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.host.in.ready)
htif.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htifW)
htif.in.bits := hio.io.in_fast.bits
hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htifW), Bool(true), htif.in.ready)
host.clk := hio.io.clk_slow
host.clk_edge := Reg(next=host.clk && !Reg(next=host.clk))
}