riscv/rocket-chip
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debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)

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This commit is contained in:
Megan Wachs 2017-06-27 13:34:55 -07:00
parent 665c2a349c
commit 56839b2c62
1 changed files with 4 additions and 6 deletions
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10
src/main/scala/rocket/CSR.scala
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@ -59,9 +59,7 @@ class DCSR extends Bundle {
val stopcycle = Bool()
val stoptime = Bool()
val cause = UInt(width = 3)
// TODO: debugint is not in the Debug Spec v13
val debugint = Bool()
val zero1 = UInt(width=2)
val zero1 = UInt(width=3)
val step = Bool()
val prv = UInt(width = PRV.SZ)
}
@ -312,7 +310,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
io.pmp := reg_pmp.map(PMP(_))
// debug interrupts are only masked by being in debug mode
when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) {
when (Bool(usingDebug) && reg_debugint && !reg_debug) {
io.interrupt := true
io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause
}
@ -506,7 +504,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive")
when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true }
when (pending_interrupts.orR || exception || reg_dcsr.debugint) { reg_wfi := false }
when (pending_interrupts.orR || exception || reg_debugint) { reg_wfi := false }
assert(!reg_wfi || io.retire === UInt(0))
when (io.retire(0) || exception) { reg_singleStepped := true }
@ -721,7 +719,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
reg_mip.mtip := io.interrupts.mtip
reg_mip.msip := io.interrupts.msip
reg_mip.meip := io.interrupts.meip
reg_dcsr.debugint := io.interrupts.debug
reg_debugint := RegInit(Bool(false), next = io.interrupts.debug)
if (!usingVM) {
reg_mideleg := 0