riscv/rocket-chip
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add vvcfg and vtcfg instructions

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This commit is contained in:
Yunsup Lee 2012-03-13 21:10:03 -07:00
parent ab6c9350db
commit 5655dbd5da
5 changed files with 101 additions and 77 deletions
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11
rocket/src/main/scala/consts.scala
View File

@ -7,7 +7,7 @@ object Constants
{ {
val HAVE_RVC = false val HAVE_RVC = false
val HAVE_FPU = true val HAVE_FPU = true
val HAVE_VEC = false val HAVE_VEC = true
val BR_N = UFix(0, 4); val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4); val BR_EQ = UFix(1, 4);
@ -142,6 +142,7 @@ object Constants
val PCR_TOHOST = UFix(16, 5); val PCR_TOHOST = UFix(16, 5);
val PCR_FROMHOST = UFix(17, 5); val PCR_FROMHOST = UFix(17, 5);
val PCR_VECBANK = UFix(18, 5); val PCR_VECBANK = UFix(18, 5);
val PCR_VECCFG = UFix(19, 5);
// temporaries for vector, these will go away // temporaries for vector, these will go away
val PCR_VEC_BACKUP = UFix(29, 5) val PCR_VEC_BACKUP = UFix(29, 5)
@ -232,9 +233,11 @@ object Constants
val VEC_N = UFix(0, 1); val VEC_N = UFix(0, 1);
val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N; val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N;
val VEC_X = UFix(0, 1) val VEC_X = UFix(0, 2)
val VEC_VL = UFix(0, 1) val VEC_FN_N = UFix(0, 2)
val VEC_CFG = UFix(1, 1) val VEC_VL = UFix(1, 2)
val VEC_CFG = UFix(2, 2)
val VEC_CFGVL = UFix(3, 2)
val VCMD_I = UFix(0, 3) val VCMD_I = UFix(0, 3)
val VCMD_F = UFix(1, 3) val VCMD_F = UFix(1, 3)

4
rocket/src/main/scala/ctrl.scala
View File

@ -261,6 +261,7 @@ object rocketCtrlDecode
// val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next // val | brtype renx2 renx1 s_alu2 dw alu | mem_cmd mem_type| mul_fn | div_fn wen s_wa s_wb | wenpcr irq sync | | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | | | |
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y), VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
VVCFG-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y), VSETVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y),
VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N), VF-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N), VMVV-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,N),
@ -305,8 +306,7 @@ object rocketCtrlDecode
VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQIMM1-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQIMM2-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N), VENQCNT-> List(VEC_Y,Y,BR_N, REN_Y,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y,N),
VWAITXCPT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y), VWAITXCPT-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y))
VWAITKILL-> List(VEC_Y,Y,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X, SYNC_N,N,N,N,N,Y))
} }
class rocketCtrl extends Component class rocketCtrl extends Component

92
rocket/src/main/scala/ctrl_vec.scala
View File

@ -12,7 +12,7 @@ class ioCtrlDpathVec extends Bundle
val appvl0 = Bool(INPUT) val appvl0 = Bool(INPUT)
val pfq = Bool(INPUT) val pfq = Bool(INPUT)
val wen = Bool(OUTPUT) val wen = Bool(OUTPUT)
val fn = Bits(1, OUTPUT) val fn = Bits(2, OUTPUT)
val sel_vcmd = Bits(3, OUTPUT) val sel_vcmd = Bits(3, OUTPUT)
val sel_vimm = Bits(1, OUTPUT) val sel_vimm = Bits(1, OUTPUT)
val sel_vimm2 = Bits(1, OUTPUT) val sel_vimm2 = Bits(1, OUTPUT)
@ -80,52 +80,52 @@ class rocketCtrlVec extends Component
// | | | | | | | | | | | | | | | | | waitxcpt // | | | | | | | | | | | | | | | | | waitxcpt
// | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | |
List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N),Array( List(N,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,N),Array(
VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFG,N,Y,Y,N,N,Y,Y,N,N,N,N,N), VVCFGIVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_CFGVL,N,Y,Y,N,N,Y,Y,N,N,N,N,N),
VVCFG-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, N,VEC_CFG, N,Y,Y,N,N,Y,Y,N,N,N,N,N),
VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N), VSETVL-> List(Y,VCMD_I, VIMM_VLEN,VIMM2_X, Y,VEC_VL, N,Y,Y,N,N,Y,Y,N,N,N,N,N),
VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N,N), VF-> List(Y,VCMD_I, VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N),
VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N,N), VMVV-> List(Y,VCMD_TX,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N),
VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,N,N,N,N,N,N,N), VMSV-> List(Y,VCMD_TX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,N,N,N,N,N,N,N),
VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_X, Y,Y,N,N,N,N,N,N,N,N,N,N), VFMVV-> List(Y,VCMD_TF,VIMM_X, VIMM2_X, N,VEC_FN_N, Y,Y,N,N,N,N,N,N,N,N,N,N),
FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N,N), FENCE_L_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N),
FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,N,N,N,N,N,N,N), FENCE_G_V-> List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,N,N,N,N,N,N,N),
FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,Y,N), FENCE_L_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N),
FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,Y,N), FENCE_G_CV->List(Y,VCMD_F, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,Y,N),
VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VLBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VSD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VSW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VSH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VSB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VFLD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VFLW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VFSD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_X, Y,Y,Y,N,N,Y,Y,N,N,N,N,N), VFSW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_X, N,VEC_FN_N, Y,Y,Y,N,N,Y,Y,N,N,N,N,N),
VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTWU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTHU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VLSTBU-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VSSTD-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VSSTW-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VSSTH-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VSSTB-> List(Y,VCMD_MX,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VFLSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VFLSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VFSSTD-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_X, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N), VFSSTW-> List(Y,VCMD_MF,VIMM_ALU, VIMM2_RS2,N,VEC_FN_N, Y,Y,Y,Y,N,Y,Y,Y,N,N,N,N),
VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_X, N,Y,N,N,N,Y,N,N,N,Y,N,N), VENQCMD-> List(Y,VCMD_A, VIMM_X, VIMM2_X, N,VEC_FN_N, N,Y,N,N,N,Y,N,N,N,Y,N,N),
VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_X, N,N,Y,N,N,N,Y,N,N,Y,N,N), VENQIMM1-> List(Y,VCMD_X, VIMM_ALU, VIMM2_X, N,VEC_FN_N, N,N,Y,N,N,N,Y,N,N,Y,N,N),
VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_X, N,N,N,Y,N,N,N,Y,N,Y,N,N), VENQIMM2-> List(Y,VCMD_X, VIMM_X, VIMM2_ALU,N,VEC_FN_N, N,N,N,Y,N,N,N,Y,N,Y,N,N),
VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,Y,N,N,N,Y,Y,N,N), VENQCNT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,Y,N,N,N,Y,Y,N,N),
VWAITXCPT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,Y), VWAITXCPT-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_FN_N, N,N,N,N,N,N,N,N,N,N,N,Y)
VWAITKILL-> List(Y,VCMD_X, VIMM_X, VIMM2_X, N,VEC_X, N,N,N,N,N,N,N,N,N,N,N,Y)
)) ))
val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs val wb_vec_val :: wb_sel_vcmd :: wb_sel_vimm :: wb_sel_vimm2 :: wb_vec_wen :: wb_vec_fn :: wb_vec_appvlmask :: veccs0 = veccs

36
rocket/src/main/scala/dpath_vec.scala
View File

@ -40,8 +40,8 @@ class rocketDpathVec extends Component
{ {
val io = new ioDpathVec() val io = new ioDpathVec()
val nxregs = Cat(UFix(0,1),io.inst(15,10).toUFix) // FIXME: to make the nregs width 7 bits val nxregs = Mux(io.ctrl.fn === VEC_CFG, io.wdata(5,0), io.inst(15,10)).toUFix + UFix(0,7)
val nfregs = io.inst(21,16).toUFix val nfregs = Mux(io.ctrl.fn === VEC_CFG, io.rs2(5,0), io.inst(21,16)).toUFix + UFix(0,7)
val nregs = nxregs + nfregs val nregs = nxregs + nfregs
val uts_per_bank = MuxLookup( val uts_per_bank = MuxLookup(
@ -104,18 +104,38 @@ class rocketDpathVec extends Component
val reg_hwvl = Reg(resetVal = UFix(32, 12)) val reg_hwvl = Reg(resetVal = UFix(32, 12))
val reg_appvl0 = Reg(resetVal = Bool(true)) val reg_appvl0 = Reg(resetVal = Bool(true))
val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0) val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)
val hwvl = Mux(io.ctrl.fn === VEC_CFG, hwvl_vcfg, reg_hwvl)
val appvl = Mux(io.wdata(11,0) < hwvl, io.wdata(11,0), hwvl).toUFix
when (io.valid && io.ctrl.wen) val hwvl =
Mux(io.ctrl.fn === VEC_CFG || io.ctrl.fn === VEC_CFGVL, hwvl_vcfg,
reg_hwvl)
val appvl =
Mux(io.ctrl.fn === VEC_CFG, UFix(0),
Mux(io.wdata(11,0) < hwvl, io.wdata(11,0).toUFix,
hwvl.toUFix))
val reg_nxregs = Reg(resetVal = UFix(32, 6))
val reg_nfregs = Reg(resetVal = UFix(32, 6))
val reg_appvl = Reg(resetVal = UFix(32, 12))
when (io.valid)
{
when (io.ctrl.fn === VEC_CFG || io.ctrl.fn === VEC_CFGVL)
{
reg_hwvl := hwvl_vcfg
reg_nxregs := nxregs
reg_nfregs := nfregs
}
when (io.ctrl.fn === VEC_VL || io.ctrl.fn === VEC_CFGVL)
{ {
when (io.ctrl.fn === VEC_CFG) { reg_hwvl := hwvl_vcfg }
reg_appvl0 := !(appvl.orR()) reg_appvl0 := !(appvl.orR())
reg_appvl := appvl
}
} }
io.wen := io.valid && io.ctrl.wen io.wen := io.valid && io.ctrl.wen
io.appvl := appvl io.appvl := appvl
val vlenm1 = appvl - Bits(1,1) val appvlm1 = appvl - UFix(1)
io.iface.vcmdq_bits := io.iface.vcmdq_bits :=
Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)), Mux(io.ctrl.sel_vcmd === VCMD_I, Cat(Bits(0,2), Bits(0,4), io.inst(9,8), Bits(0,6), Bits(0,6)),
@ -128,7 +148,7 @@ class rocketDpathVec extends Component
Bits(0,20)))))))) Bits(0,20))))))))
io.iface.vximm1q_bits := io.iface.vximm1q_bits :=
Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, io.inst(21,10), vlenm1(10,0)), Mux(io.ctrl.sel_vimm === VIMM_VLEN, Cat(Bits(0,29), io.vecbankcnt, io.vecbank, nfregs, nxregs, appvlm1(10,0)),
io.wdata) // VIMM_ALU io.wdata) // VIMM_ALU
io.iface.vximm2q_bits := io.iface.vximm2q_bits :=

3
rocket/src/main/scala/instructions.scala
View File

@ -244,6 +244,8 @@ object Instructions
val VFMTS = Bits("b?????_?????_?????_0000110010_1110011",32); val VFMTS = Bits("b?????_?????_?????_0000110010_1110011",32);
val VVCFGIVL = Bits("b?????_?????_????????????_001_1110011",32); val VVCFGIVL = Bits("b?????_?????_????????????_001_1110011",32);
val VTCFGIVL = Bits("b?????_?????_????????????_011_1110011",32); val VTCFGIVL = Bits("b?????_?????_????????????_011_1110011",32);
val VVCFG = Bits("b00000_?????_?????_0000001000_1110011",32);
val VTCFG = Bits("b00000_?????_?????_0000011000_1110011",32);
val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32); val VSETVL = Bits("b?????_?????_000000000000_101_1110011",32);
val VF = Bits("b00000_?????_????????????_111_1110011",32); val VF = Bits("b00000_?????_????????????_111_1110011",32);
// vector supervisor instructions // vector supervisor instructions
@ -252,7 +254,6 @@ object Instructions
val VENQIMM2 = Bits("b00000_?????_?????_1000000010_1111011",32) val VENQIMM2 = Bits("b00000_?????_?????_1000000010_1111011",32)
val VENQCNT = Bits("b00000_?????_?????_1000000011_1111011",32) val VENQCNT = Bits("b00000_?????_?????_1000000011_1111011",32)
val VWAITXCPT = Bits("b00000_00000_00000_1100000000_1111011",32) val VWAITXCPT = Bits("b00000_00000_00000_1100000000_1111011",32)
val VWAITKILL = Bits("b00000_00000_00000_1100000001_1111011",32)
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32); val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);
} }