diff --git a/src/main/scala/coreplex/UnitTest.scala b/src/main/scala/coreplex/UnitTest.scala
index b308b2e1..ca8e66da 100644
--- a/src/main/scala/coreplex/UnitTest.scala
+++ b/src/main/scala/coreplex/UnitTest.scala
@@ -7,10 +7,14 @@ import uncore.tilelink.TLId
 import cde.Parameters
 
 class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
-  require(!tc.hasExtMMIOPort)
   require(tc.nSlaves == 0)
   require(tc.nMemChannels == 0)
 
+  io.master.mmio.foreach { port =>
+    port.acquire.valid := Bool(false)
+    port.grant.ready := Bool(false)
+  }
+
   io.debug.req.ready := Bool(false)
   io.debug.resp.valid := Bool(false)