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util: add the IdentityModule, useful to dedup wires

This commit is contained in:
Wesley W. Terpstra 2017-09-06 16:07:31 -07:00
parent 1a87ed1193
commit 5626cdd18f

View File

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// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import Chisel._
class IdentityModule[T <: Data](gen: T) extends Module
{
val io = new Bundle {
val in = gen.cloneType.flip
val out = gen.cloneType
}
io.out := io.in
}
object IdentityModule
{
def apply[T <: Data](x: T): T = {
val identity = Module(new IdentityModule(x))
identity.io.in := x
identity.io.out
}
}