riscv/rocket-chip
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make sure wmask is passed for PutBlock in broadcast hub

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This commit is contained in:
Howard Mao 2015-11-20 14:09:24 -08:00
parent 941b64cd62
commit 55a85cc67a
2 changed files with 5 additions and 1 deletions
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5
uncore/src/main/scala/broadcast.scala
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@ -270,7 +270,8 @@ class BroadcastAcquireTracker(trackerId: Int)
client_xact_id = UInt(trackerId), client_xact_id = UInt(trackerId),
addr_block = xact.addr_block, addr_block = xact.addr_block,
addr_beat = oacq_data_cnt, addr_beat = oacq_data_cnt,
data = xact.data_buffer(oacq_data_cnt))(outerParams) data = xact.data_buffer(oacq_data_cnt),
wmask = xact.wmask_buffer(oacq_data_cnt))(outerParams)
val oacq_read_beat = Get( val oacq_read_beat = Get(
client_xact_id = UInt(trackerId), client_xact_id = UInt(trackerId),
@ -317,6 +318,7 @@ class BroadcastAcquireTracker(trackerId: Int)
io.inner.acquire.ready := Bool(true) io.inner.acquire.ready := Bool(true)
when(io.inner.acquire.valid) { when(io.inner.acquire.valid) {
xact.data_buffer(io.iacq().addr_beat) := io.iacq().data xact.data_buffer(io.iacq().addr_beat) := io.iacq().data
xact.wmask_buffer(io.iacq().addr_beat) := io.iacq().wmask()
iacq_data_valid := iacq_data_valid.bitSet(io.iacq().addr_beat, Bool(true)) iacq_data_valid := iacq_data_valid.bitSet(io.iacq().addr_beat, Bool(true))
} }
when(iacq_data_done) { collect_iacq_data := Bool(false) } when(iacq_data_done) { collect_iacq_data := Bool(false) }
@ -334,6 +336,7 @@ class BroadcastAcquireTracker(trackerId: Int)
when(io.inner.acquire.valid) { when(io.inner.acquire.valid) {
xact := io.iacq() xact := io.iacq()
xact.data_buffer(UInt(0)) := io.iacq().data xact.data_buffer(UInt(0)) := io.iacq().data
xact.wmask_buffer(UInt(0)) := io.iacq().wmask()
collect_iacq_data := io.iacq().hasMultibeatData() collect_iacq_data := io.iacq().hasMultibeatData()
iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat
val needs_probes = mask_incoherent.orR val needs_probes = mask_incoherent.orR

1
uncore/src/main/scala/tilelink.scala
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@ -137,6 +137,7 @@ trait HasTileLinkData extends HasTileLinkBeatId {
/** An entire cache block of data */ /** An entire cache block of data */
trait HasTileLinkBlock extends HasTileLinkParameters { trait HasTileLinkBlock extends HasTileLinkParameters {
val data_buffer = Vec(tlDataBeats, UInt(width = tlDataBits)) val data_buffer = Vec(tlDataBeats, UInt(width = tlDataBits))
val wmask_buffer = Vec(tlDataBeats, UInt(width = tlWriteMaskBits))
} }
/** The id of a client source or destination. Used in managers. */ /** The id of a client source or destination. Used in managers. */