riscv/rocket-chip
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changed coherence type width names to represent max sizes for all protocols

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This commit is contained in:
Henry Cook
2012-04-04 13:57:08 -07:00
parent 0b4937f70f
commit 551e09c9d5
3 changed files with 14 additions and 14 deletions
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8
rocket/src/main/scala/consts.scala
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@ -197,10 +197,10 @@ object Constants
val GLOBAL_XACT_ID_BITS = 2
val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
val X_INIT_TYPE_BITS = 2
val X_REP_TYPE_BITS = 3
val P_REQ_TYPE_BITS = 2
val P_REP_TYPE_BITS = 3
val X_INIT_TYPE_MAX_BITS = 2
val X_REP_TYPE_MAX_BITS = 3
val P_REQ_TYPE_MAX_BITS = 2
val P_REP_TYPE_MAX_BITS = 3
// external memory interface
val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)