riscv/rocket-chip
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Add (unused) RV32 CSRs

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This commit is contained in:
Andrew Waterman
2014-03-15 17:33:17 -07:00
parent 943d7ac80a
commit 54cbf0c4f1
1 changed files with 12 additions and 0 deletions
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12
rocket/src/main/scala/instructions.scala
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@@ -260,6 +260,10 @@ object CSRs {
val uarch13 = 0xccd val uarch13 = 0xccd
val uarch14 = 0xcce val uarch14 = 0xcce
val uarch15 = 0xccf val uarch15 = 0xccf
val counth = 0x586
val cycleh = 0xc80
val timeh = 0xc81
val instreth = 0xc82
val all = { val all = {
val res = collection.mutable.ArrayBuffer[Int]() val res = collection.mutable.ArrayBuffer[Int]()
res += fflags res += fflags
@@ -306,4 +310,12 @@ object CSRs {
res += uarch15 res += uarch15
res.toArray res.toArray
} }
val all32 = {
val res = collection.mutable.ArrayBuffer(all:_*)
res += counth
res += cycleh
res += timeh
res += instreth
res.toArray
}
} }