hack fence.g.cv to support waiting the control processor

2012-03-02 02:10:26 -08:00
parent 1054cec087
commit 54baa0713c
2 changed files with 52 additions and 43 deletions
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@ -193,6 +193,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
    // exceptions
    vu.io.cpu_exception.addr := dpath.io.vec_iface.eaddr.toUFix
    vu.io.cpu_exception.exception := dpath.io.vec_iface.exception
+    ctrl.io.vec_iface.exception_done := vu.io.done

    // hooking up vector memory interface
    val storegen = new StoreDataGen