From 5498468743cc5dba87d280631de9b7c47741e267 Mon Sep 17 00:00:00 2001
From: Henry Styles <hes@sifive.com>
Date: Fri, 29 Sep 2017 15:40:39 -0700
Subject: [PATCH] FPU : simplify pipeline register generation in FMA

---
 src/main/scala/tile/FPU.scala | 49 ++++++++++++-----------------------
 1 file changed, 17 insertions(+), 32 deletions(-)

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index 1c990777..f64fbd2c 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -579,42 +579,27 @@ class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
     val valid_stage0 = Wire(Bool())
     val roundingMode_stage0 = Wire(UInt(width=3))
     val detectTininess_stage0 = Wire(UInt(width=1))
-   
-    if(latency>0) {
-      mulAddRecFNToRaw_postMul.io.fromPreMul   := RegEnable(mulAddRecFNToRaw_preMul.io.toPostMul,io.validin)
-      mulAddRecFNToRaw_postMul.io.mulAddResult := RegEnable(mulAddResult,io.validin)
-      mulAddRecFNToRaw_postMul.io.roundingMode := RegEnable(io.roundingMode,io.validin)  
-      roundingMode_stage0                      := RegEnable(io.roundingMode,io.validin) 
-      detectTininess_stage0                    := RegEnable(io.detectTininess,io.validin)
-      valid_stage0                             := RegNext(io.validin,false.B)
-    } else {
-      mulAddRecFNToRaw_postMul.io.fromPreMul   := mulAddRecFNToRaw_preMul.io.toPostMul
-      mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
-      mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
-      roundingMode_stage0                      := io.roundingMode
-      detectTininess_stage0                    := io.detectTininess
-      valid_stage0                             := io.validin
-    }
- 
+  
+    val postmul_regs = if(latency>0) 1 else 0
+    mulAddRecFNToRaw_postMul.io.fromPreMul   := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
+    mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
+    mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
+    roundingMode_stage0                      := Pipe(io.validin, io.roundingMode, postmul_regs).bits
+    detectTininess_stage0                    := Pipe(io.validin, io.detectTininess, postmul_regs).bits
+    valid_stage0                             := Pipe(io.validin, false.B, postmul_regs).valid
+    
     //------------------------------------------------------------------------
     //------------------------------------------------------------------------
     val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
-    //
-    if(latency==2){
-      roundRawFNToRecFN.io.invalidExc         := RegEnable(mulAddRecFNToRaw_postMul.io.invalidExc,valid_stage0)
-      roundRawFNToRecFN.io.in                 := RegEnable(mulAddRecFNToRaw_postMul.io.rawOut,valid_stage0)
-      roundRawFNToRecFN.io.roundingMode       := RegEnable(roundingMode_stage0,valid_stage0)
-      roundRawFNToRecFN.io.detectTininess     := RegEnable(detectTininess_stage0,valid_stage0)
-      io.validout                             := RegNext(valid_stage0, false.B)
-    } else {
-      roundRawFNToRecFN.io.invalidExc         := mulAddRecFNToRaw_postMul.io.invalidExc
-      roundRawFNToRecFN.io.in                 := mulAddRecFNToRaw_postMul.io.rawOut
-      roundRawFNToRecFN.io.roundingMode       := roundingMode_stage0
-      roundRawFNToRecFN.io.detectTininess     := detectTininess_stage0
-      io.validout                             := valid_stage0
-    }
 
-    roundRawFNToRecFN.io.infiniteExc    := Bool(false)
+    val round_regs = if(latency==2) 1 else 0
+    roundRawFNToRecFN.io.invalidExc         := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
+    roundRawFNToRecFN.io.in                 := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
+    roundRawFNToRecFN.io.roundingMode       := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
+    roundRawFNToRecFN.io.detectTininess     := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
+    io.validout                             := Pipe(valid_stage0, false.B, round_regs).valid
+
+    roundRawFNToRecFN.io.infiniteExc := Bool(false)
 
     io.out            := roundRawFNToRecFN.io.out
     io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags