Make more require statements in diplomacy verbose (#693)

* diplomacy: add more verbose requirements
* bump firrtl

firrtl

@@ -1 +1 @@
-Subproject commit bda2bd363fbe66de9425bba12d96f5f9816a43ce
+Subproject commit 25a0500dca7e83381739483886c462d7a87721a0

src/main/scala/diplomacy/AddressDecoder.scala

@@ -27,7 +27,7 @@ object AddressDecoder
       // Verify the user did not give us an impossible problem
       nonEmptyPorts.combinations(2).foreach { case Seq(x, y) =>
         x.foreach { a => y.foreach { b =>
-          require (!a.overlaps(b)) // it must be possible to disambiguate ports!
+          require (!a.overlaps(b), s"Ports cannot overlap: $a $b")
         } }
       }
 
@@ -43,7 +43,7 @@ object AddressDecoder
       // Verify that it remains possible to disambiguate all ports
       widePorts.combinations(2).foreach { case Seq(x, y) =>
         x.foreach { a => y.foreach { b =>
-          require (!a.overlaps(b))
+          require (!a.overlaps(b), s"Ports cannot overlap: $a $b")
         } }
       }
 

src/main/scala/diplomacy/Parameters.scala

@@ -127,7 +127,7 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
   def contiguous = alignment == mask+1
 
   def finite = mask >= 0
-  def max = { require (finite); base | mask }
+  def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
 
   // Widen the match function to ignore all bits in imask
   def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
@@ -160,7 +160,7 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
   }
 
   def toRanges = {
-    require (finite)
+    require (finite, "Ranges cannot be calculated on infinite mask")
     val size = alignment
     val fragments = mask & ~(size-1)
     val bits = bitIndexes(fragments)
@@ -222,7 +222,7 @@ object AddressSet
 
 case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
 {
-  require (depth >= 0)
+  require (depth >= 0, "Buffer depth must be >= 0")
   def isDefined = depth > 0
   def latency = if (isDefined && !flow) 1 else 0
 }