riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

groundtest: make it happy with TL2 addressing

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-10-27 19:55:40 -07:00
parent 9a26cb7ec7
commit 545154c1c3
3 changed files with 6 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/uncore/tilelink2/Legacy.scala
View File

@ -38,11 +38,9 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
require (m.supportsPutPartial.contains(TransferSizes(1, tlDataBytes)))
require (m.supportsPutPartial.contains(TransferSizes(tlDataBeats * tlDataBytes)))
}
// Any atomic support => must support 32-bit up to beat size of all types
if (m.supportsArithmetic || m.supportsLogical) {
require (m.supportsArithmetic.contains(TransferSizes(4, tlDataBytes)))
require (m.supportsLogical .contains(TransferSizes(4, tlDataBytes)))
}
// Any atomic support => must support 32-bit size
if (m.supportsArithmetic) { require (m.supportsArithmetic.contains(TransferSizes(4))) }
if (m.supportsLogical) { require (m.supportsLogical .contains(TransferSizes(4))) }
// We straight-up require hints
require (edge.manager.allSupportHint)
}