riscv/rocket-chip
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balance MultiChannel router correctly

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This commit is contained in:
Howard Mao
2015-10-26 12:23:03 -07:00
parent 3270d17ad3
commit 5440d6c2ae
1 changed files with 4 additions and 1 deletions
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5
junctions/src/main/scala/nasti.scala
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@@ -469,9 +469,12 @@ object NastiMultiChannelRouter {
Vec(master)
} else {
val dataBytes = p(MIFDataBits) * p(MIFDataBeats) / 8
val selOffset = log2Up(dataBytes)
val selBits = log2Ceil(nChannels)
// Consecutive blocks route to alternating channels
val routeSel = (addr: UInt) => {
Vec.tabulate(nChannels)(i => addr(selBits - 1, 0) === UInt(i)).toBits
val sel = addr(selOffset + selBits - 1, selOffset)
Vec.tabulate(nChannels)(i => sel === UInt(i)).toBits
}
val router = Module(new NastiRouter(nChannels, routeSel))
router.io.master <> master