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Convert frontend and icache to diplomacy/tl2 (#486)

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* [rocket] file capitalization

* [rocket] cacheDataBits &etc in HasCoreParameters

* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters

* [rocket] frontend and icache now diplomatic
This commit is contained in:
Henry Cook
2016-12-12 17:38:55 -08:00
committed by GitHub
parent 5244fc8433
commit 540502f96d
9 changed files with 106 additions and 94 deletions
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5
src/main/scala/rocket/rocket.scala
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@ -5,7 +5,7 @@ package rocket
import Chisel._
import uncore.devices._
import uncore.util.CacheName
import uncore.util.{CacheName, CacheBlockBytes}
import uncore.constants._
import uncore.tilelink2._
import util._
@ -40,7 +40,6 @@ trait HasCoreParameters {
val xLen = p(XLen)
val fLen = xLen // TODO relax this
val edge = p(TLCacheEdge)
val usingVM = p(UseVM)
val usingUser = p(UseUser) || usingVM
val usingDebug = p(UseDebug)
@ -70,7 +69,7 @@ trait HasCoreParameters {
def pgIdxBits = 12
def pgLevelBits = 10 - log2Ceil(xLen / 32)
def vaddrBits = pgIdxBits + pgLevels * pgLevelBits
val paddrBits = edge.bundle.addressBits
val paddrBits = p(TLCacheEdge).bundle.addressBits
def ppnBits = paddrBits - pgIdxBits
def vpnBits = vaddrBits - pgIdxBits
val pgLevels = p(PgLevels)