Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself

src/main/scala/rocketchip/Configs.scala

@@ -116,7 +116,7 @@ class BasePlatformConfig extends Config (
       }
       case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
       case NExtTopInterrupts => 2
-      case NExtPeripheryInterrupts => 0
+      case NExtPeripheryInterrupts => site(ExtraDevices).nInterrupts
       // Note that PLIC asserts that this is > 0.
       case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
       case AsyncDebugBus => false
@@ -269,7 +269,6 @@ class WithTestRAM extends Config(
           extra: Bundle, p: Parameters) {
           val testram = Module(new TileLinkTestRAM(ramSize)(p))
           testram.io <> mmioPorts("testram")
-          interrupts.foreach(x => x := Bool(false))
         }
       }
       new TestRAMDevice

src/main/scala/rocketchip/Devices.scala

@@ -14,6 +14,10 @@ abstract class DeviceBlock {
   def nClientPorts: Int
   /** Address map entries for all of the devices */
   def addrMapEntries: Seq[AddrMapEntry]
+  /**
+   * The total number of interrupt signals coming 
+   *  from all the devices                       */
+  def nInterrupts : Int = 0
 
   /**
    * The function that elaborates all the extra devices and connects them
@@ -48,6 +52,8 @@ abstract class DeviceBlock {
        "}\n"
     }.mkString
   }
+
+
 }
 
 class EmptyDeviceBlock extends DeviceBlock {

src/main/scala/rocketchip/TestConfigs.scala

@@ -196,7 +196,6 @@ class WithBusMasterTest extends Config(
           val busmaster = Module(new ExampleBusMaster()(p))
           busmaster.io.mmio <> mmioPorts("busmaster")
           clientPorts.head <> busmaster.io.mem
-          interrupts.foreach(x => x := Bool(false))
         }
       }
       new BusMasterDevice