Incorporate feedback to make the NExtPerhipheryInterrupts come from DeviceBlock itself
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41aa80c5d7
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@ -116,7 +116,7 @@ class BasePlatformConfig extends Config (
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}
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case NExtTopInterrupts => 2
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case NExtPeripheryInterrupts => 0
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case NExtPeripheryInterrupts => site(ExtraDevices).nInterrupts
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// Note that PLIC asserts that this is > 0.
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case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
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case AsyncDebugBus => false
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@ -269,7 +269,6 @@ class WithTestRAM extends Config(
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extra: Bundle, p: Parameters) {
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val testram = Module(new TileLinkTestRAM(ramSize)(p))
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testram.io <> mmioPorts("testram")
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interrupts.foreach(x => x := Bool(false))
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}
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}
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new TestRAMDevice
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@ -14,6 +14,10 @@ abstract class DeviceBlock {
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def nClientPorts: Int
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/** Address map entries for all of the devices */
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def addrMapEntries: Seq[AddrMapEntry]
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/**
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* The total number of interrupt signals coming
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* from all the devices */
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def nInterrupts : Int = 0
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/**
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* The function that elaborates all the extra devices and connects them
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@ -48,6 +52,8 @@ abstract class DeviceBlock {
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"}\n"
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}.mkString
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}
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}
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class EmptyDeviceBlock extends DeviceBlock {
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@ -196,7 +196,6 @@ class WithBusMasterTest extends Config(
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val busmaster = Module(new ExampleBusMaster()(p))
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busmaster.io.mmio <> mmioPorts("busmaster")
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clientPorts.head <> busmaster.io.mem
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interrupts.foreach(x => x := Bool(false))
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}
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}
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new BusMasterDevice
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