parameterize broadcast hub by # of tiles
This commit is contained in:
Andrew Waterman
parent
1258f31825
commit
53d69d3006
@ -234,14 +234,14 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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}
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class XactTracker(id: Int) extends Component with FourStateCoherence {
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class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherence {
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val io = new Bundle {
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq }.flip
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val p_data = (new ioPipe) { new TrackerProbeData }
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val p_rep_cnt_dec = Bits(ntiles, INPUT)
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val p_req_cnt_inc = Bits(ntiles, INPUT)
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val p_rep_data = (new ioPipe) { new ProbeReplyData }.flip
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val x_init_data = (new ioPipe) { new TransactionInitData }.flip
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val sent_x_rep_ack = Bool(INPUT)
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@ -259,13 +259,13 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
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val t_type = Bits(X_INIT_TYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_p_rep_dep = Bits(NTILES, OUTPUT)
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val pop_x_init = Bits(NTILES, OUTPUT)
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val pop_x_init_data = Bits(NTILES, OUTPUT)
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val pop_x_init_dep = Bits(NTILES, OUTPUT)
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val push_p_req = Bits(ntiles, OUTPUT)
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val pop_p_rep = Bits(ntiles, OUTPUT)
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val pop_p_rep_data = Bits(ntiles, OUTPUT)
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val pop_p_rep_dep = Bits(ntiles, OUTPUT)
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val pop_x_init = Bits(ntiles, OUTPUT)
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val pop_x_init_data = Bits(ntiles, OUTPUT)
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val pop_x_init_dep = Bits(ntiles, OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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@ -319,8 +319,8 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val p_rep_count = if (NTILES == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(NTILES)))
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val p_req_flags = Reg(resetVal = Bits(0, width = NTILES))
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val p_rep_count = if (ntiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(ntiles)))
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val p_req_flags = Reg(resetVal = Bits(0, width = ntiles))
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val p_rep_tile_id_ = Reg{ Bits() }
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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@ -336,7 +336,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.init_tile_id := init_tile_id_
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io.p_rep_tile_id := p_rep_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.sharer_count := UFix(ntiles) // TODO: Broadcast only
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io.t_type := t_type_
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io.mem_req_cmd.valid := Bool(false)
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@ -350,13 +350,13 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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io.probe_req.bits.p_type := sendProbeReqType(t_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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io.probe_req.bits.address := addr_
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io.push_p_req := Bits(0, width = NTILES)
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io.pop_p_rep := Bits(0, width = NTILES)
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io.pop_p_rep_data := Bits(0, width = NTILES)
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io.pop_p_rep_dep := Bits(0, width = NTILES)
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io.pop_x_init := Bits(0, width = NTILES)
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io.pop_x_init_data := Bits(0, width = NTILES)
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io.pop_x_init_dep := Bits(0, width = NTILES)
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io.push_p_req := Bits(0, width = ntiles)
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io.pop_p_rep := Bits(0, width = ntiles)
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io.pop_p_rep_data := Bits(0, width = ntiles)
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io.pop_p_rep_dep := Bits(0, width = ntiles)
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io.pop_x_init := Bits(0, width = ntiles)
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io.pop_x_init_data := Bits(0, width = ntiles)
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io.pop_x_init_dep := Bits(0, width = ntiles)
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io.send_x_rep_ack := Bool(false)
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switch (state) {
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@ -368,7 +368,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
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x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
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if(NTILES > 1) p_rep_count := UFix(NTILES-1)
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if(ntiles > 1) p_rep_count := UFix(ntiles-1)
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p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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@ -388,7 +388,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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when(io.p_rep_cnt_dec.orR) {
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val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
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io.pop_p_rep := io.p_rep_cnt_dec
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if(NTILES > 1) p_rep_count := p_rep_count_next
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if(ntiles > 1) p_rep_count := p_rep_count_next
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when(p_rep_count === UFix(0)) {
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io.pop_p_rep := Bool(true)
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state := s_mem
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@ -440,14 +440,14 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
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}
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}
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abstract class CoherenceHub extends Component with CoherencePolicy {
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abstract class CoherenceHub(ntiles: Int) extends Component with CoherencePolicy {
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }.flip
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val tiles = Vec(ntiles) { new ioTileLink() }.flip
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val mem = new ioMem
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}
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}
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class CoherenceHubNull extends CoherenceHub {
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class CoherenceHubNull extends CoherenceHub(1) {
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val x_init = io.tiles(0).xact_init
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val is_write = x_init.bits.t_type === X_INIT_WRITE_UNCACHED
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@ -474,7 +474,7 @@ class CoherenceHubNull extends CoherenceHub {
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}
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class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourStateCoherence{
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = (addr1 === addr2)
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@ -487,7 +487,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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))
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(ntiles, _))
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val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
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@ -498,8 +498,8 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
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val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
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val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(ntiles){ Wire(){Bool()} } }
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val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bits(width = TILE_ID_BITS)} }
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val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
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@ -523,17 +523,17 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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sent_x_rep_ack_arr(i) := Bool(false)
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p_data_tile_id_arr(i) := Bits(0, width = TILE_ID_BITS)
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p_data_valid_arr(i) := Bool(false)
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for( j <- 0 until NTILES) {
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for( j <- 0 until ntiles) {
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p_rep_cnt_dec_arr(i)(j) := Bool(false)
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p_req_cnt_inc_arr(i)(j) := Bool(false)
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}
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}
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val p_rep_data_dep_list = List.fill(NTILES)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth must >= NPRIMARY
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val x_init_data_dep_list = List.fill(NTILES)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth should >= NPRIMARY
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val p_rep_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth must >= NPRIMARY
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val x_init_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS, true)){new TrackerDependency}) // depth should >= NPRIMARY
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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for( j <- 0 until ntiles ) {
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val finish = io.tiles(j).xact_finish
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do_free_arr(finish.bits.global_xact_id) := finish.valid
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finish.ready := Bool(true)
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@ -543,7 +543,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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// Forward memory responses from mem to tile or arbitrate to ack
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val mem_idx = io.mem.resp.bits.tag
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val ack_idx = PriorityEncoder(send_x_rep_ack_arr.toBits)
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for( j <- 0 until NTILES ) {
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for( j <- 0 until ntiles ) {
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val rep = io.tiles(j).xact_rep
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rep.bits.t_type := UFix(0)
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rep.bits.tile_xact_id := UFix(0)
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@ -583,7 +583,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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io.mem.req_data <> mem_req_data_arb.io.out
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// Handle probe replies, which may or may not have data
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for( j <- 0 until NTILES ) {
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for( j <- 0 until ntiles ) {
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val p_rep = io.tiles(j).probe_rep
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val p_rep_data = io.tiles(j).probe_rep_data
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val idx = p_rep.bits.global_xact_id
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@ -601,10 +601,10 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.valid
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trackerList(i).io.p_rep_data.bits := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.bits
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trackerList(i).io.p_rep_data_dep.valid := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.valid, (0 until NTILES).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.valid))
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trackerList(i).io.p_rep_data_dep.bits := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.bits))
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trackerList(i).io.p_rep_data_dep.valid := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.valid, (0 until ntiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.valid))
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trackerList(i).io.p_rep_data_dep.bits := MuxLookup(trackerList(i).io.p_rep_tile_id, p_rep_data_dep_list(0).io.deq.bits, (0 until ntiles).map( j => UFix(j) -> p_rep_data_dep_list(j).io.deq.bits))
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for( j <- 0 until NTILES) {
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for( j <- 0 until ntiles) {
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val p_rep = io.tiles(j).probe_rep
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p_rep_cnt_dec_arr(i)(j) := p_rep.valid && (p_rep.bits.global_xact_id === UFix(i))
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}
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@ -612,9 +612,9 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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// Nack conflicting transaction init attempts
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val s_idle :: s_abort_drain :: s_abort_send :: s_abort_complete :: Nil = Enum(4){ UFix() }
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val abort_state_arr = Vec(NTILES) { Reg(resetVal = s_idle) }
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val want_to_abort_arr = Vec(NTILES) { Wire() { Bool()} }
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for( j <- 0 until NTILES ) {
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val abort_state_arr = Vec(ntiles) { Reg(resetVal = s_idle) }
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val want_to_abort_arr = Vec(ntiles) { Wire() { Bool()} }
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for( j <- 0 until ntiles ) {
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val x_init = io.tiles(j).xact_init
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val x_init_data = io.tiles(j).xact_init_data
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val x_abort = io.tiles(j).xact_abort
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@ -662,7 +662,7 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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// Only one allocation per cycle
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// Init requests may or may not have data
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val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
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val init_arb = (new Arbiter(NTILES)) { new TrackerAllocReq() }
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val init_arb = (new Arbiter(ntiles)) { new TrackerAllocReq() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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alloc_arb.io.in(i).valid := !trackerList(i).io.busy
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trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready
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@ -671,10 +671,10 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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trackerList(i).io.x_init_data.bits := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.bits
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trackerList(i).io.x_init_data.valid := io.tiles(trackerList(i).io.init_tile_id).xact_init_data.valid
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trackerList(i).io.x_init_data_dep.bits := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.bits, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
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trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.valid, (0 until NTILES).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid))
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trackerList(i).io.x_init_data_dep.bits := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.bits, (0 until ntiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.bits))
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trackerList(i).io.x_init_data_dep.valid := MuxLookup(trackerList(i).io.init_tile_id, x_init_data_dep_list(0).io.deq.valid, (0 until ntiles).map( j => UFix(j) -> x_init_data_dep_list(j).io.deq.valid))
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}
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for( j <- 0 until NTILES ) {
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for( j <- 0 until ntiles ) {
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val x_init = io.tiles(j).xact_init
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val x_init_data = io.tiles(j).xact_init_data
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val x_init_data_dep = x_init_data_dep_list(j).io.deq
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@ -694,8 +694,8 @@ class CoherenceHubBroadcast extends CoherenceHub with FourStateCoherence{
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// Handle probe request generation
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// Must arbitrate for each request port
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val p_req_arb_arr = List.fill(NTILES)((new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() })
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for( j <- 0 until NTILES ) {
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val p_req_arb_arr = List.fill(ntiles)((new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() })
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for( j <- 0 until ntiles ) {
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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p_req_arb_arr(j).io.in(i).bits := t.probe_req.bits
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