diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index d435daca..56755e42 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -386,7 +386,7 @@ class FPU extends CoreModule
   when (load_wb) { 
     regfile(load_wb_tag) := load_wb_data_recoded 
     if (EnableCommitLog) {
-      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data)
+      printf ("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + UInt(32), load_wb_data) // TODO see what happens, either change spike to sext, or us or whatever.
     }
   }
 
@@ -464,7 +464,7 @@ class FPU extends CoreModule
   val winfo = Reg(Vec(Bits(), maxLatency-1))
   val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
   val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, ex_reg_valid)
-  val mem_winfo = Cat(mem_ctrl.single, pipeid(mem_ctrl), mem_reg_inst(11,7))
+  val mem_winfo = Cat(pipeid(mem_ctrl), mem_ctrl.single, mem_reg_inst(11,7)) //single only used for debugging
 
   for (i <- 0 until maxLatency-2) {
     when (wen(i+1)) { winfo(i) := winfo(i+1) }
@@ -482,16 +482,17 @@ class FPU extends CoreModule
   }
 
   val waddr = Mux(divSqrt_wen, divSqrt_waddr, winfo(0)(4,0).toUInt)
-  val wsrc = (winfo(0) >> 5)(1,0) // TODO: get rid of magic number on log(num_pipes)
+  val wsrc = (winfo(0) >> 6)
   val wdata = Mux(divSqrt_wen, divSqrt_wdata, Vec(pipes.map(_.wdata))(wsrc))
   val wexc = Vec(pipes.map(_.wexc))(wsrc)
-  when (wen(0) || divSqrt_wen) { 
+  when (wen(0) || divSqrt_wen) {
     regfile(waddr) := wdata 
     if (EnableCommitLog) {
       val wdata_unrec_s = hardfloat.recodedFloatNToFloatN(wdata(64,0), 23, 9)
       val wdata_unrec_d = hardfloat.recodedFloatNToFloatN(wdata(64,0), 52, 12)
-      val wb_single = (winfo(0) >> 5)(2) // TODO: get rid of magic numbers
-      printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32), Mux(wb_single, wdata_unrec_s, wdata_unrec_d))
+      val wb_single = (winfo(0) >> 5)(0)
+      printf ("f%d p%d 0x%x\n", waddr, waddr+ UInt(32),
+        Mux(wb_single, Cat(Fill(32, wdata_unrec_s(31)), wdata_unrec_s), wdata_unrec_d))
     }
   }