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Bump chisel3 and firrtl, add support for firrtl $ delimiter

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This commit is contained in:
jackkoenig 2016-03-25 17:20:19 -07:00 committed by Howard Mao
parent 38649bd4c1
commit 5378f79b50
7 changed files with 85 additions and 74 deletions
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2
Makefrag
View File

@ -14,7 +14,7 @@ SBT := CHISEL_SUBMODULE="chisel$(CHISEL_VERSION)" java -Xmx2048M -Xss8M -XX:MaxP
SHELL := /bin/bash SHELL := /bin/bash
ifeq ($(CHISEL_VERSION),2) ifeq ($(CHISEL_VERSION),2)
CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) $(CHISEL_VERSION) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
else else
CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
endif endif

2
chisel3

@ -1 +1 @@
Subproject commit e6ee1ddb79c219e313e530a029d8402274fbaebc Subproject commit 189bdb436162890da29d06c931b48e7b0c179e49

2
firrtl

@ -1 +1 @@
Subproject commit 8ae6ece99dfadb8d3dd25acc3549a975e3c40bbc Subproject commit 77578a6ab0ebf1c538aadb5792626cbac62fbfdc

136
src/main/scala/TestBench.scala
View File

@ -7,7 +7,11 @@ import Chisel._
object TestBenchGeneration extends FileSystemUtilities { object TestBenchGeneration extends FileSystemUtilities {
def generateVerilogFragment( def generateVerilogFragment(
topModuleName: String, configClassName: String, topModuleName: String, configClassName: String,
nMemChannel: Int) = { nMemChannel: Int, chiselVersion: Int) = {
// Chisel 3 uses $ during name expansion whereas Chisel 2 uses _
require(chiselVersion == 2 || chiselVersion == 3)
val delim = if (chiselVersion == 3) "$" else "_"
// YUNSUP: // YUNSUP:
// I originally wrote this using a 2d wire array, but of course Synopsys' // I originally wrote this using a 2d wire array, but of course Synopsys'
@ -163,54 +167,54 @@ object TestBenchGeneration extends FileSystemUtilities {
""" } mkString """ } mkString
val nasti_connections = (0 until nMemChannel) map { i => s""" val nasti_connections = (0 until nMemChannel) map { i => s"""
.io_mem_${i}_ar_valid (ar_valid_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}valid (ar_valid_delay_$i),
.io_mem_${i}_ar_ready (ar_ready_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}ready (ar_ready_delay_$i),
.io_mem_${i}_ar_bits_addr (ar_addr_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}addr (ar_addr_delay_$i),
.io_mem_${i}_ar_bits_id (ar_id_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}id (ar_id_delay_$i),
.io_mem_${i}_ar_bits_size (ar_size_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}size (ar_size_delay_$i),
.io_mem_${i}_ar_bits_len (ar_len_delay_$i), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}len (ar_len_delay_$i),
.io_mem_${i}_ar_bits_burst (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}burst (),
.io_mem_${i}_ar_bits_lock (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}lock (),
.io_mem_${i}_ar_bits_cache (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}cache (),
.io_mem_${i}_ar_bits_prot (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}prot (),
.io_mem_${i}_ar_bits_qos (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}qos (),
.io_mem_${i}_ar_bits_region (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}region (),
.io_mem_${i}_ar_bits_user (), .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}user (),
.io_mem_${i}_aw_valid (aw_valid_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}valid (aw_valid_delay_$i),
.io_mem_${i}_aw_ready (aw_ready_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}ready (aw_ready_delay_$i),
.io_mem_${i}_aw_bits_addr (aw_addr_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}addr (aw_addr_delay_$i),
.io_mem_${i}_aw_bits_id (aw_id_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}id (aw_id_delay_$i),
.io_mem_${i}_aw_bits_size (aw_size_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}size (aw_size_delay_$i),
.io_mem_${i}_aw_bits_len (aw_len_delay_$i), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}len (aw_len_delay_$i),
.io_mem_${i}_aw_bits_burst (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}burst (),
.io_mem_${i}_aw_bits_lock (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}lock (),
.io_mem_${i}_aw_bits_cache (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}cache (),
.io_mem_${i}_aw_bits_prot (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}prot (),
.io_mem_${i}_aw_bits_qos (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}qos (),
.io_mem_${i}_aw_bits_region (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}region (),
.io_mem_${i}_aw_bits_user (), .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}user (),
.io_mem_${i}_w_valid (w_valid_delay_$i), .io${delim}mem${delim}${i}${delim}w${delim}valid (w_valid_delay_$i),
.io_mem_${i}_w_ready (w_ready_delay_$i), .io${delim}mem${delim}${i}${delim}w${delim}ready (w_ready_delay_$i),
.io_mem_${i}_w_bits_strb (w_strb_delay_$i), .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}strb (w_strb_delay_$i),
.io_mem_${i}_w_bits_data (w_data_delay_$i), .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}data (w_data_delay_$i),
.io_mem_${i}_w_bits_last (w_last_delay_$i), .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}last (w_last_delay_$i),
.io_mem_${i}_w_bits_user (), .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}user (),
.io_mem_${i}_r_valid (r_valid_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}valid (r_valid_delay_$i),
.io_mem_${i}_r_ready (r_ready_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}ready (r_ready_delay_$i),
.io_mem_${i}_r_bits_resp (r_resp_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}resp (r_resp_delay_$i),
.io_mem_${i}_r_bits_id (r_id_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}id (r_id_delay_$i),
.io_mem_${i}_r_bits_data (r_data_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}data (r_data_delay_$i),
.io_mem_${i}_r_bits_last (r_last_delay_$i), .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}last (r_last_delay_$i),
.io_mem_${i}_r_bits_user (1'b0), .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}user (1'b0),
.io_mem_${i}_b_valid (b_valid_delay_$i), .io${delim}mem${delim}${i}${delim}b${delim}valid (b_valid_delay_$i),
.io_mem_${i}_b_ready (b_ready_delay_$i), .io${delim}mem${delim}${i}${delim}b${delim}ready (b_ready_delay_$i),
.io_mem_${i}_b_bits_resp (b_resp_delay_$i), .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}resp (b_resp_delay_$i),
.io_mem_${i}_b_bits_id (b_id_delay_$i), .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}id (b_id_delay_$i),
.io_mem_${i}_b_bits_user (1'b0), .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}user (1'b0),
""" } mkString """ } mkString
@ -229,35 +233,35 @@ object TestBenchGeneration extends FileSystemUtilities {
$nasti_connections $nasti_connections
`ifndef FPGA `ifndef FPGA
.io_host_clk(htif_clk), .io${delim}host${delim}clk(htif_clk),
.io_host_clk_edge(), .io${delim}host${delim}clk_edge(),
.io_host_debug_stats_csr(htif_out_stats_delay), .io${delim}host${delim}debug_stats_csr(htif_out_stats_delay),
`ifdef MEM_BACKUP_EN `ifdef MEM_BACKUP_EN
.io_mem_backup_ctrl_en(1'b1), .io${delim}mem_backup_ctrl${delim}en(1'b1),
`else `else
.io_mem_backup_ctrl_en(1'b0), .io${delim}mem_backup_ctrl${delim}en(1'b0),
`endif // MEM_BACKUP_EN `endif // MEM_BACKUP_EN
.io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay), .io${delim}mem_backup_ctrl${delim}in_valid(mem_bk_in_valid_delay),
.io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay), .io${delim}mem_backup_ctrl${delim}out_ready(mem_bk_out_ready_delay),
.io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay), .io${delim}mem_backup_ctrl${delim}out_valid(mem_bk_out_valid_delay),
`else `else
.io_host_clk (), .io${delim}host${delim}clk (),
.io_host_clk_edge (), .io${delim}host${delim}clk_edge (),
.io_host_debug_stats_csr (), .io${delim}host${delim}debug_stats_csr (),
.io_mem_backup_ctrl_en (1'b0), .io${delim}mem_backup_ctrl${delim}en (1'b0),
.io_mem_backup_ctrl_in_valid (1'b0), .io${delim}mem_backup_ctrl${delim}in_valid (1'b0),
.io_mem_backup_ctrl_out_ready (1'b0), .io${delim}mem_backup_ctrl${delim}out_ready (1'b0),
.io_mem_backup_ctrl_out_valid (), .io${delim}mem_backup_ctrl${delim}out_valid (),
`endif // FPGA `endif // FPGA
.io_host_in_valid(htif_in_valid_delay), .io${delim}host${delim}in${delim}valid(htif_in_valid_delay),
.io_host_in_ready(htif_in_ready_delay), .io${delim}host${delim}in${delim}ready(htif_in_ready_delay),
.io_host_in_bits(htif_in_bits_delay), .io${delim}host${delim}in${delim}bits(htif_in_bits_delay),
.io_host_out_valid(htif_out_valid_delay), .io${delim}host${delim}out${delim}valid(htif_out_valid_delay),
.io_host_out_ready(htif_out_ready_delay), .io${delim}host${delim}out${delim}ready(htif_out_ready_delay),
.io_host_out_bits(htif_out_bits_delay) .io${delim}host${delim}out${delim}bits(htif_out_bits_delay)
); );
""" """

9
src/main/scala/Testing.scala
View File

@ -187,6 +187,12 @@ object TestGenerator extends App with FileSystemUtilities {
val projectName = args(0) val projectName = args(0)
val topModuleName = args(1) val topModuleName = args(1)
val configClassName = args(2) val configClassName = args(2)
val chiselVersion = try {
args(3).toInt
} catch {
case e => throwException("4th argument must be CHISEL_VERSION")
}
require(chiselVersion == 2 || chiselVersion == 3)
val config = try { val config = try {
Class.forName(s"$projectName.$configClassName").newInstance.asInstanceOf[Config] Class.forName(s"$projectName.$configClassName").newInstance.asInstanceOf[Config]
} catch { } catch {
@ -209,7 +215,8 @@ object TestGenerator extends App with FileSystemUtilities {
TestGeneration.generateMakefrag(topModuleName, configClassName) TestGeneration.generateMakefrag(topModuleName, configClassName)
TestBenchGeneration.generateVerilogFragment( TestBenchGeneration.generateVerilogFragment(
topModuleName, configClassName, topModuleName, configClassName,
paramsFromConfig(NMemoryChannels)) paramsFromConfig(NMemoryChannels),
chiselVersion)
TestBenchGeneration.generateCPPFragment( TestBenchGeneration.generateCPPFragment(
topModuleName, configClassName, topModuleName, configClassName,
paramsFromConfig(NMemoryChannels)) paramsFromConfig(NMemoryChannels))

2
vsim/Makefrag
View File

@ -46,7 +46,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(sim_dir)/libdramsim.a \ $(sim_dir)/libdramsim.a \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).verbose \ +define+PRINTF_COND="$(TB).verbose && !$(TB).reset" \
+libext+.v \ +libext+.v \
#-------------------------------------------------------------------- #--------------------------------------------------------------------

6
vsim/Makefrag-verilog
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@ -11,14 +11,14 @@ $(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(ge
fi fi
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)" cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) $(CHISEL_VERSION) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
else else
FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
$(FIRRTL): $(FIRRTL):
$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build $(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build-scala
# If I don't mark these as .SECONDARY then make will delete these internal # If I don't mark these as .SECONDARY then make will delete these internal
# files. # files.
@ -27,7 +27,7 @@ $(FIRRTL):
$(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs) $(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem" cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_VERSION) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@ mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@
$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL) $(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)