riscv/rocket-chip
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Merge pull request #757 from freechipsproject/isp-port

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Inter-System-Port
This commit is contained in:
Henry Cook
2017-06-15 13:07:19 -07:00
committed by GitHub
parent 2665a3eb2f b1917e7915
commit 5368ea60fe
9 changed files with 393 additions and 90 deletions
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5
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -13,6 +13,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val module: CoreplexNetworkModule
def bindingTree: ResourceMap
val tile_splitter = LazyModule(new TLSplitter)
val l1tol2 = LazyModule(new TLXbar)
val l1tol2_beatBytes = l1tol2Config.beatBytes
val l1tol2_lineBytes = p(CacheBlockBytes)
@ -34,6 +36,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
private val l2in_buffer = LazyModule(new TLBuffer)
private val l2in_fifo = LazyModule(new TLFIFOFixer)
l1tol2.node :=* l2in_fifo.node
l1tol2.node :=* tile_splitter.node
l2in_fifo.node :=* l2in_buffer.node
l2in_buffer.node :=* l2in
@ -83,7 +86,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
}
// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
lazy val topManagers = Some(ManagerUnification(l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
lazy val topManagers = Some(ManagerUnification(tile_splitter.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
ResourceBinding {
val managers = topManagers.get
val max = managers.flatMap(_.address).map(_.max).max

44
src/main/scala/coreplex/ISPPort.scala Normal file
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@ -0,0 +1,44 @@
// See LICENSE.SiFive for license details.
package coreplex
import Chisel._
import config._
import diplomacy._
import rocket._
import tile._
import uncore.tilelink2._
import util._
trait HasISPPort extends CoreplexNetwork {
val module: HasISPPortModule
// TODO: use ChipLink instead of AsyncTileLink
val isp_in = TLAsyncInputNode()
val isp_out = TLAsyncOutputNode()
private val out_xbar = LazyModule(new TLXbar)
private val out_nums = LazyModule(new TLNodeNumberer)
private val out_async = LazyModule(new TLAsyncCrossingSource)
out_xbar.node :=* tile_splitter.node
out_nums.node :*= out_xbar.node
out_async.node :*= out_nums.node
isp_out :*= out_async.node
private val in_async = LazyModule(new TLAsyncCrossingSink)
in_async.node :=* isp_in
l1tol2.node :=* in_async.node
}
trait HasISPPortBundle extends CoreplexNetworkBundle {
val outer: HasISPPort
// TODO: move to IO(...) in Module?
val isp_in = outer.isp_in.bundleIn
val isp_out = outer.isp_out.bundleOut
}
trait HasISPPortModule extends CoreplexNetworkModule {
val outer: HasISPPort
val io: HasISPPortBundle
}

8
src/main/scala/coreplex/RocketTiles.scala
View File

@ -36,7 +36,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val pWithExtra = p.alterPartial {
case TileKey => c
case BuildRoCC => c.rocc
case SharedMemoryTLEdge => l1tol2.node.edgesIn(0)
case SharedMemoryTLEdge => tile_splitter.node.edgesIn(0)
}
val asyncIntXbar = LazyModule(new IntXbar)
@ -64,7 +64,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
buffer.node :=* wrapper.masterNode
fixer.node :=* buffer.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= cbus.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode
@ -82,7 +82,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= source.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode
@ -102,7 +102,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode
fixer.node :=* sink.node
l1tol2.node :=* fixer.node
tile_splitter.node :=* fixer.node
wrapper.slaveNode :*= source.node
wrapper.asyncIntNode := asyncIntXbar.intnode
wrapper.periphIntNode := periphIntXbar.intnode