riscv/rocket-chip
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MPRV takes effect regardless of privilege mode

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This commit is contained in:
Andrew Waterman 2016-05-02 19:48:39 -07:00
parent 5cbcc41515
commit 5352497edb
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/tlb.scala
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@ -125,7 +125,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val plru = new PseudoLRU(entries) val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace) val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
val do_mprv = io.ptw.status.prv === PRV.M && io.ptw.status.mprv && !io.req.bits.instruction val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv) val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S val priv_uses_vm = priv <= PRV.S