finished xact_finish and xact_abort transactors in coherence hub
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@ -205,7 +205,9 @@ class CoherenceHubNoDir extends CoherenceHub {
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trackerList(i).io.xact_finish := free_arr.read(UFix(i))
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}
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// In parallel, every cycle: nack conflicting transactions, free finished ones
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// Nack conflicting transaction init attempts
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val aborting = Wire() { Bits(width = NTILES) }
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val initiating = Wire() { Bits(width = NTILES) }
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for( j <- 0 until NTILES ) {
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val init = io.tiles(j).xact_init
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val abort = io.tiles(j).xact_abort
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@ -214,34 +216,16 @@ class CoherenceHubNoDir extends CoherenceHub {
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val t = trackerList(i).io
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conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address)
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}
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abort.valid := init.valid && (conflicts.orR || busy_arr.flatten().andR)
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aborting(j) := (conflicts.orR || busy_arr.flatten().andR)
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abort.valid := init.valid && aborting
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abort.bits.tileTransactionID := init.bits.tileTransactionID
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// TODO:
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// Reg(aborted) := (abort.ready && abort.valid)
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// Reg(allocated) : = had_priority(j) & !(abort.ready && abort.valid)
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// init.rdy = aborted || allocated
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init.ready := aborting(j) || initiating(j)
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}
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/*
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// Todo: which implementation is clearer?
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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val freed = Bits(width = NTILES)
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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free(j) := finish.valid && (UFix(i) === finish.bits.globalTransactionID)
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finish.ready := Bool(true) // finsh.pop()
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}
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t.xact_finish := freed.orR
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}
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*/
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free_arr := Bits(0, width=NGLOBAL_XACTS)
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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when(finish.valid) {
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free_arr.write(finish.bits.globalTransactionID, Bool(true))
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}
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free_arr.write(finish.bits.globalTransactionID, finish.valid)
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finish.ready := Bool(true)
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}
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