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Configs: use a uniform syntax without Match exceptions (#507)

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* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
This commit is contained in:
Wesley W. Terpstra 2017-01-13 14:41:19 -08:00 committed by Henry Cook
parent b448387899
commit 52bb6cd9d9
5 changed files with 405 additions and 549 deletions
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44
src/main/scala/config/Config.scala
View File

@ -3,9 +3,6 @@
package config package config
class Field[T] class Field[T]
class CDEMatchError() extends Exception {
override def fillInStackTrace() = this
}
abstract class View { abstract class View {
final def apply[T](pname: Field[T]): T = apply(pname, this) final def apply[T](pname: Field[T]): T = apply(pname, this)
@ -15,38 +12,28 @@ abstract class View {
} }
abstract class Parameters extends View { abstract class Parameters extends View {
final def ++ (x: Parameters): Parameters = new ChainParameters(this, x) final def ++ (x: Parameters): Parameters = new ChainParameters(this, x)
final def alter(f: (Any, View, View, View) => Any): Parameters = Parameters(f) ++ this final def alter(f: (View, View, View) => PartialFunction[Any,Any]): Parameters = Parameters(f) ++ this
final def alter(m: Map[Any,Any]): Parameters = Parameters(m) ++ this final def alterPartial(f: PartialFunction[Any,Any]): Parameters = Parameters((_,_,_) => f) ++ this
final def alter(f: PartialFunction[Any,Any]): Parameters = Parameters(f) ++ this
final def alterPartial(f: PartialFunction[Any,Any]): Parameters = Parameters(f) ++ this
protected[config] def chain(site: View, tail: View, pname: Any): Any protected[config] def chain(site: View, tail: View, pname: Any): Any
protected[config] def find(pname: Any, site: View) = chain(site, new TerminalView, pname) protected[config] def find(pname: Any, site: View) = chain(site, new TerminalView, pname)
} }
object Parameters { object Parameters {
def empty: Parameters = new EmptyParameters def empty: Parameters = new EmptyParameters
def apply(f: (Any, View, View, View) => Any): Parameters = new FunctionParameters(f) def apply(f: (View, View, View) => PartialFunction[Any,Any]): Parameters = new PartialParameters(f)
def apply(m: Map[Any,Any]): Parameters = new MapParameters(m)
def apply(f: PartialFunction[Any,Any]): Parameters = new PartialParameters(f)
def partial(f: PartialFunction[Any,Any]): Parameters = new PartialParameters(f)
def root(p: Parameters) = p def root(p: Parameters) = p
} }
class Config(p: Parameters) extends Parameters { class Config(p: Parameters) extends Parameters {
def this(f: (Any, View, View) => Any) = this(Parameters((p,s,h,u) => f(p,s,h))) // backwards compat; don't use def this(f: (View, View, View) => PartialFunction[Any,Any]) = this(Parameters(f))
def this(f: (Any, View, View, View) => Any) = this(Parameters(f))
def this(m: Map[Any,Any]) = this(Parameters(m))
def this(f: PartialFunction[Any,Any]) = this(Parameters(f))
protected[config] def chain(site: View, tail: View, pname: Any) = p.chain(site, tail, pname) protected[config] def chain(site: View, tail: View, pname: Any) = p.chain(site, tail, pname)
override def toString = this.getClass.getSimpleName override def toString = this.getClass.getSimpleName
def toInstance = this def toInstance = this
} }
class ConfigPartial(f: PartialFunction[Any,Any]) extends Config(Parameters(f))
// Internal implementation: // Internal implementation:
private class TerminalView extends View { private class TerminalView extends View {
@ -66,22 +53,9 @@ private class EmptyParameters extends Parameters {
def chain(site: View, tail: View, pname: Any) = tail.find(pname, site) def chain(site: View, tail: View, pname: Any) = tail.find(pname, site)
} }
private class FunctionParameters(f: (Any, View, View, View) => Any) extends Parameters { private class PartialParameters(f: (View, View, View) => PartialFunction[Any,Any]) extends Parameters {
protected[config] def chain(site: View, tail: View, pname: Any) = { protected[config] def chain(site: View, tail: View, pname: Any) = {
try f(pname, site, this, tail) val g = f(site, this, tail)
catch { if (g.isDefinedAt(pname)) g.apply(pname) else tail.find(pname, site)
case e: CDEMatchError => tail.find(pname, site)
case e: scala.MatchError => tail.find(pname, site)
}
} }
} }
private class MapParameters(map: Map[Any, Any]) extends Parameters {
protected[config] def chain(site: View, tail: View, pname: Any) =
map.get(pname).getOrElse(find(pname, site))
}
private class PartialParameters(f: PartialFunction[Any,Any]) extends Parameters {
protected[config] def chain(site: View, tail: View, pname: Any) =
if (f.isDefinedAt(pname)) f.apply(pname) else tail.find(pname, site)
}

423
src/main/scala/coreplex/Configs.scala
View File

@ -17,179 +17,151 @@ import uncore.converters._
import uncore.util._ import uncore.util._
import util._ import util._
class BaseCoreplexConfig extends Config ( class BaseCoreplexConfig extends Config ((site, here, up) => {
{ (pname,site,here) => //Memory Parameters
lazy val innerDataBits = site(XLen) case PAddrBits => 32
lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
pname match { case ASIdBits => 7
//Memory Parameters //Params used by all caches
case PAddrBits => 32 case CacheName("L1I") => CacheConfig(
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */ nSets = 64,
case ASIdBits => 7 nWays = 4,
//Params used by all caches rowBits = site(L1toL2Config).beatBytes*8,
case CacheName("L1I") => CacheConfig( nTLBEntries = 8,
nSets = 64, cacheIdBits = 0,
nWays = 4, splitMetadata = false)
rowBits = site(L1toL2Config).beatBytes*8, case CacheName("L1D") => CacheConfig(
nTLBEntries = 8, nSets = 64,
cacheIdBits = 0, nWays = 4,
splitMetadata = false) rowBits = site(L1toL2Config).beatBytes*8,
case CacheName("L1D") => CacheConfig( nTLBEntries = 8,
nSets = 64, cacheIdBits = 0,
nWays = 4, splitMetadata = false)
rowBits = site(L1toL2Config).beatBytes*8, case ECCCode => None
nTLBEntries = 8, case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays)
cacheIdBits = 0, //L1InstCache
splitMetadata = false) case BtbKey => BtbParameters()
case ECCCode => None //L1DataCache
case Replacer => () => new RandomReplacement(site(site(CacheName)).nWays) case DCacheKey => DCacheConfig(nMSHRs = 2)
//L1InstCache case DataScratchpadSize => 0
case BtbKey => BtbParameters() //L2 Memory System Params
//L1DataCache case AmoAluOperandBits => site(XLen)
case DCacheKey => DCacheConfig(nMSHRs = 2) case NAcquireTransactors => 7
case DataScratchpadSize => 0 case L2StoreDataQueueDepth => 1
//L2 Memory System Params case L2DirectoryRepresentation => new NullRepresentation(site(NTiles))
case AmoAluOperandBits => site(XLen) //Tile Constants
case NAcquireTransactors => 7 case BuildRoCC => Nil
case L2StoreDataQueueDepth => 1 case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case L2DirectoryRepresentation => new NullRepresentation(site(NTiles)) case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
//Tile Constants //Rocket Core Constants
case BuildRoCC => Nil case CoreInstBits => if (site(UseCompressed)) 16 else 32
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _) case FetchWidth => if (site(UseCompressed)) 2 else 1
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _) case RetireWidth => 1
//Rocket Core Constants case UseVM => true
case CoreInstBits => if (site(UseCompressed)) 16 else 32 case UseUser => false
case FetchWidth => if (site(UseCompressed)) 2 else 1 case UseDebug => true
case RetireWidth => 1 case NBreakpoints => 1
case UseVM => true case NPerfCounters => 0
case UseUser => false case NPerfEvents => 0
case UseDebug => true case FastLoadWord => true
case NBreakpoints => 1 case FastLoadByte => false
case NPerfCounters => 0 case FastJAL => false
case NPerfEvents => 0 case XLen => 64
case FastLoadWord => true case FPUKey => Some(FPUConfig())
case FastLoadByte => false case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
case FastJAL => false case UseAtomics => true
case XLen => 64 case UseCompressed => true
case FPUKey => Some(FPUConfig()) case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)) case NCustomMRWCSRs => 0
case UseAtomics => true case MtvecInit => Some(BigInt(0))
case UseCompressed => true case MtvecWritable => true
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen)) //Uncore Paramters
case NCustomMRWCSRs => 0 case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
case MtvecInit => Some(BigInt(0)) case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
case MtvecWritable => true log2Up(site(TLKey(site(TLId))).nClients)
//Uncore Paramters case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) + case TLKey("L1toL2") => {
log2Up(site(TLKey(site(TLId))).nClients) val useMEI = site(NTiles) <= 1
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8) TileLinkParameters(
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth coherencePolicy = (
case TLKey("L1toL2") => { if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
val useMEI = site(NTiles) <= 1 else new MESICoherence(site(L2DirectoryRepresentation))),
TileLinkParameters( nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */,
coherencePolicy = ( nCachingClients = 1,
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation)) nCachelessClients = 1,
else new MESICoherence(site(L2DirectoryRepresentation))), maxClientXacts = List(
nManagers = site(BankedL2Config).nBanks + 1 /* MMIO */, // L1 cache
nCachingClients = 1, site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
nCachelessClients = 1, // RoCC
maxClientXacts = List( if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max,
// L1 cache maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
site(DCacheKey).nMSHRs + 1 /* IOMSHR */, maxManagerXacts = site(NAcquireTransactors) + 2,
// RoCC dataBeats = (8 * site(CacheBlockBytes)) / site(XLen),
if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)).max, dataBits = site(CacheBlockBytes)*8)
maxClientsPerPort = if (site(BuildRoCC).isEmpty) 1 else 2,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
}
case BootROMFile => "./bootrom/bootrom.img"
case NTiles => 1
case BroadcastConfig => BroadcastConfig()
case BankedL2Config => BankedL2Config()
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
case EnableL2Logging => false
case _ => throw new CDEMatchError
}
} }
) case BootROMFile => "./bootrom/bootrom.img"
case NTiles => 1
case BroadcastConfig => BroadcastConfig()
case BankedL2Config => BankedL2Config()
case CacheBlockBytes => 64
case CacheBlockOffsetBits => log2Up(site(CacheBlockBytes))
case EnableL2Logging => false
})
class WithNCores(n: Int) extends Config( class WithNCores(n: Int) extends Config((site, here, up) => {
(pname,site,here) => pname match { case NTiles => n
case NTiles => n })
case _ => throw new CDEMatchError
})
class WithNBanksPerMemChannel(n: Int) extends Config( class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n) })
case _ => throw new CDEMatchError
})
class WithNTrackersPerBank(n: Int) extends Config( class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n) })
case _ => throw new CDEMatchError
})
// This is the number of sets **per way** // This is the number of sets **per way**
class WithL1ICacheSets(sets: Int) extends Config( class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets) })
case _ => throw new CDEMatchError
})
// This is the number of sets **per way** // This is the number of sets **per way**
class WithL1DCacheSets(sets: Int) extends Config( class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets) })
case _ => throw new CDEMatchError
})
class WithL1ICacheWays(ways: Int) extends Config( class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways) })
case _ => throw new CDEMatchError
})
class WithL1DCacheWays(ways: Int) extends Config( class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways) })
case _ => throw new CDEMatchError
})
class WithCacheBlockBytes(linesize: Int) extends Config( class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
(pname,site,here) => pname match { case CacheBlockBytes => linesize
case CacheBlockBytes => linesize })
case _ => throw new CDEMatchError
})
class WithDataScratchpad(n: Int) extends Config( class WithDataScratchpad(n: Int) extends Config((site, here, up) => {
(pname,site,here,up) => pname match { case DataScratchpadSize => n
case DataScratchpadSize => n case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes)) })
case _ => throw new CDEMatchError
})
// TODO: re-add L2 // TODO: re-add L2
class WithL2Cache extends Config( class WithL2Cache extends Config((site, here, up) => {
(pname,site,here) => pname match { case CacheName("L2") => CacheConfig(
case CacheName("L2") => CacheConfig( nSets = 1024,
nSets = 1024, nWays = 1,
nWays = 1, rowBits = site(L1toL2Config).beatBytes*8,
rowBits = site(L1toL2Config).beatBytes*8, nTLBEntries = 0,
nTLBEntries = 0, cacheIdBits = 1,
cacheIdBits = 1, splitMetadata = false)
splitMetadata = false) })
case _ => throw new CDEMatchError
})
class WithBufferlessBroadcastHub extends Config( class WithBufferlessBroadcastHub extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true) })
})
/** /**
* WARNING!!! IGNORE AT YOUR OWN PERIL!!! * WARNING!!! IGNORE AT YOUR OWN PERIL!!!
@ -203,103 +175,74 @@ class WithBufferlessBroadcastHub extends Config(
* system depends on coherence between channels in any way, * system depends on coherence between channels in any way,
* DO NOT use this configuration. * DO NOT use this configuration.
*/ */
class WithStatelessBridge extends Config( class WithStatelessBridge extends Config((site, here, up) => {
(pname,site,here,up) => pname match {
/* !!! FIXME /* !!! FIXME
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) => case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
val pass = LazyModule(new TLBuffer(0)(site)) val pass = LazyModule(new TLBuffer(0)(site))
(pass.node, pass.node) (pass.node, pass.node)
}) })
*/ */
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0) case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case _ => throw new CDEMatchError })
})
class WithPLRU extends Config( class WithL2Capacity(size_kb: Int) extends Config(Parameters.empty)
(pname, site, here) => pname match {
case _ => throw new CDEMatchError
})
class WithL2Capacity(size_kb: Int) extends Config( class WithNL2Ways(n: Int) extends Config((site, here, up) => {
(pname,site,here) => pname match { case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
case _ => throw new CDEMatchError })
})
class WithNL2Ways(n: Int) extends Config( class WithRV32 extends Config((site, here, up) => {
(pname,site,here,up) => pname match { case XLen => 32
case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n) case FPUKey => Some(FPUConfig(divSqrt = false))
}) })
class WithRV32 extends Config( class WithBlockingL1 extends Config((site, here, up) => {
(pname,site,here) => pname match { case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case XLen => 32 })
case FPUKey => Some(FPUConfig(divSqrt = false))
case _ => throw new CDEMatchError
})
class WithBlockingL1 extends Config( class WithSmallCores extends Config((site, here, up) => {
(pname,site,here,up) => pname match { case MulDivKey => Some(MulDivConfig())
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0) case FPUKey => None
case _ => throw new CDEMatchError case UseVM => false
}) case BtbKey => BtbParameters(nEntries = 0)
case NAcquireTransactors => 2
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
})
class WithSmallCores extends Config( class WithRoccExample extends Config((site, here, up) => {
(pname,site,here,up) => pname match { case BuildRoCC => Seq(
case MulDivKey => Some(MulDivConfig()) RoccParameters(
case FPUKey => None opcodes = OpcodeSet.custom0,
case UseVM => false generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
case BtbKey => BtbParameters(nEntries = 0) RoccParameters(
case NAcquireTransactors => 2 opcodes = OpcodeSet.custom1,
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4) generator = (p: Parameters) => Module(new TranslatorExample()(p)),
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4) nPTWPorts = 1),
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0) RoccParameters(
case _ => throw new CDEMatchError opcodes = OpcodeSet.custom2,
}) generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
class WithRoccExample extends Config( case RoccMaxTaggedMemXacts => 1
(pname, site, here) => pname match { })
case BuildRoCC => Seq(
RoccParameters(
opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
RoccParameters(
opcodes = OpcodeSet.custom1,
generator = (p: Parameters) => Module(new TranslatorExample()(p)),
nPTWPorts = 1),
RoccParameters(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
case RoccMaxTaggedMemXacts => 1 class WithDefaultBtb extends Config((site, here, up) => {
case _ => throw new CDEMatchError case BtbKey => BtbParameters()
}) })
class WithDefaultBtb extends Config( class WithFastMulDiv extends Config((site, here, up) => {
(pname,site,here) => pname match { case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))
case BtbKey => BtbParameters() })
case _ => throw new CDEMatchError
})
class WithFastMulDiv extends Config( class WithoutMulDiv extends Config((site, here, up) => {
(pname,site,here) => pname match { case MulDivKey => None
case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)) })
case _ => throw new CDEMatchError
})
class WithoutMulDiv extends Config( class WithoutFPU extends Config((site, here, up) => {
(pname, site, here) => pname match { case FPUKey => None
case MulDivKey => None })
case _ => throw new CDEMatchError
})
class WithoutFPU extends Config( class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
(pname, site, here) => pname match { case FPUKey => Some(FPUConfig(divSqrt = false))
case FPUKey => None })
case _ => throw new CDEMatchError
})
class WithFPUWithoutDivSqrt extends Config (
(pname, site, here) => pname match {
case FPUKey => Some(FPUConfig(divSqrt = false))
case _ => throw new CDEMatchError
})

232
src/main/scala/groundtest/Configs.scala
View File

@ -45,7 +45,7 @@ class FancyMemtestConfig extends Config(
new WithL2Cache ++ new GroundTestConfig) new WithL2Cache ++ new GroundTestConfig)
class CacheFillTestConfig extends Config( class CacheFillTestConfig extends Config(
new WithNL2Ways(4) ++ new WithL2Capacity(4) ++ new WithCacheFillTest ++ new WithPLRU ++ new WithL2Cache ++ new GroundTestConfig) new WithNL2Ways(4) ++ new WithL2Capacity(4) ++ new WithCacheFillTest ++ new WithL2Cache ++ new GroundTestConfig)
class BroadcastRegressionTestConfig extends Config( class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig) new WithBroadcastRegressionTest ++ new GroundTestConfig)
@ -73,137 +73,117 @@ class Edge32BitMemtestConfig extends Config(
new WithEdgeDataBits(32) ++ new MemtestConfig) new WithEdgeDataBits(32) ++ new MemtestConfig)
/* Composable Configs to set individual parameters */ /* Composable Configs to set individual parameters */
class WithGroundTest extends Config( class WithGroundTest extends Config((site, here, up) => {
(pname, site, here) => pname match { case TLKey("L1toL2") => {
case TLKey("L1toL2") => { val useMEI = site(NTiles) <= 1
val useMEI = site(NTiles) <= 1 val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen) TileLinkParameters(
TileLinkParameters( coherencePolicy = (
coherencePolicy = ( if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation)) else new MESICoherence(site(L2DirectoryRepresentation))),
else new MESICoherence(site(L2DirectoryRepresentation))), nManagers = site(BankedL2Config).nBanks + 1,
nManagers = site(BankedL2Config).nBanks + 1, nCachingClients = 1,
nCachingClients = 1, nCachelessClients = 1,
nCachelessClients = 1, maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +: site(GroundTestKey).map(_.maxXacts))
site(GroundTestKey).map(_.maxXacts)) .reduce(max(_, _)),
.reduce(max(_, _)), maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum,
maxClientsPerPort = site(GroundTestKey).map(_.uncached).sum, maxManagerXacts = site(NAcquireTransactors) + 2,
maxManagerXacts = site(NAcquireTransactors) + 2, dataBeats = dataBeats,
dataBeats = dataBeats, dataBits = site(CacheBlockBytes)*8)
dataBits = site(CacheBlockBytes)*8) }
} case FPUKey => None
case FPUKey => None case UseAtomics => false
case UseAtomics => false case UseCompressed => false
case UseCompressed => false })
case _ => throw new CDEMatchError
})
class WithComparator extends Config( class WithComparator extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 2)
GroundTestTileSettings(uncached = 2) }
} case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new ComparatorCore()(p))
(p: Parameters) => Module(new ComparatorCore()(p)) case ComparatorKey => ComparatorParameters(
case ComparatorKey => ComparatorParameters( targets = Seq(site(ExtMem).base, testRamAddr),
targets = Seq(site(ExtMem).base, testRamAddr), width = 8,
width = 8, operations = 1000,
operations = 1000, atomics = site(UseAtomics),
atomics = site(UseAtomics), prefetches = false)
prefetches = false) case FPUConfig => None
case FPUConfig => None case UseAtomics => false
case UseAtomics => false })
case _ => throw new CDEMatchError
})
class WithAtomics extends Config( class WithAtomics extends Config((site, here, up) => {
(pname, site, here) => pname match { case UseAtomics => true
case UseAtomics => true })
case _ => throw new CDEMatchError
})
class WithPrefetches extends Config( class WithPrefetches extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true)
case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true) })
case _ => throw new CDEMatchError
})
class WithMemtest extends Config( class WithMemtest extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(1, 1)
GroundTestTileSettings(1, 1) }
} case GeneratorKey => TrafficGeneratorParameters(
case GeneratorKey => TrafficGeneratorParameters( maxRequests = 128,
maxRequests = 128, startAddress = BigInt(site(ExtMem).base))
startAddress = BigInt(site(ExtMem).base)) case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new GeneratorTest()(p))
(p: Parameters) => Module(new GeneratorTest()(p)) })
case _ => throw new CDEMatchError
})
class WithNGenerators(nUncached: Int, nCached: Int) extends Config( class WithNGenerators(nUncached: Int, nCached: Int) extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(nUncached, nCached)
GroundTestTileSettings(nUncached, nCached) }
} })
case _ => throw new CDEMatchError
})
class WithCacheFillTest extends Config( class WithCacheFillTest extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 1)
GroundTestTileSettings(uncached = 1) }
} case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new CacheFillTest()(p))
(p: Parameters) => Module(new CacheFillTest()(p)) })
case _ => throw new CDEMatchError
})
class WithBroadcastRegressionTest extends Config( class WithBroadcastRegressionTest extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(1, 1, maxXacts = 3)
GroundTestTileSettings(1, 1, maxXacts = 3) }
} case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new RegressionTest()(p))
(p: Parameters) => Module(new RegressionTest()(p)) case GroundTestRegressions =>
case GroundTestRegressions => (p: Parameters) => RegressionTests.broadcastRegressions(p)
(p: Parameters) => RegressionTests.broadcastRegressions(p) })
case _ => throw new CDEMatchError
})
class WithCacheRegressionTest extends Config( class WithCacheRegressionTest extends Config((site, here, up) => {
(pname, site, here) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(1, 1, maxXacts = 5)
GroundTestTileSettings(1, 1, maxXacts = 5) }
} case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new RegressionTest()(p))
(p: Parameters) => Module(new RegressionTest()(p)) case GroundTestRegressions =>
case GroundTestRegressions => (p: Parameters) => RegressionTests.cacheRegressions(p)
(p: Parameters) => RegressionTests.cacheRegressions(p) })
case _ => throw new CDEMatchError
})
class WithTraceGen extends Config( class WithTraceGen extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case GroundTestKey => Seq.fill(site(NTiles)) {
case GroundTestKey => Seq.fill(site(NTiles)) { GroundTestTileSettings(uncached = 1, cached = 1)
GroundTestTileSettings(uncached = 1, cached = 1) }
} case BuildGroundTest =>
case BuildGroundTest => (p: Parameters) => Module(new GroundTestTraceGenerator()(p))
(p: Parameters) => Module(new GroundTestTraceGenerator()(p)) case GeneratorKey => TrafficGeneratorParameters(
case GeneratorKey => TrafficGeneratorParameters( maxRequests = 8192,
maxRequests = 8192, startAddress = 0)
startAddress = 0) case AddressBag => {
case AddressBag => { val nSets = 2
val nSets = 2 val nWays = 1
val nWays = 1 val blockOffset = site(CacheBlockOffsetBits)
val blockOffset = site(CacheBlockOffsetBits) val nBeats = site(TLKey("L1toL2")).dataBeats
val nBeats = site(TLKey("L1toL2")).dataBeats List.tabulate(4 * nWays) { i =>
List.tabulate(4 * nWays) { i => Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) } }.flatten
}.flatten }
} case UseAtomics => true
case UseAtomics => true case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 16, nWays = 1)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 16, nWays = 1) })
case _ => throw new CDEMatchError
})

133
src/main/scala/rocketchip/Configs.scala
View File

@ -19,25 +19,23 @@ import scala.collection.immutable.HashMap
import DefaultTestSuites._ import DefaultTestSuites._
import config._ import config._
class BasePlatformConfig extends Config( class BasePlatformConfig extends Config((site, here, up) => {
(pname,site,here) => pname match { // TileLink connection parameters
// TileLink connection parameters case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args))) case TLFuzzReadyValid => false
case TLFuzzReadyValid => false case TLCombinationalCheck => false
case TLCombinationalCheck => false //Memory Parameters
//Memory Parameters case NExtTopInterrupts => 2
case NExtTopInterrupts => 2 case SOCBusConfig => site(L1toL2Config)
case SOCBusConfig => site(L1toL2Config) case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
case PeripheryBusConfig => TLBusConfig(beatBytes = 4) case PeripheryBusArithmetic => true
case PeripheryBusArithmetic => true // Note that PLIC asserts that this is > 0.
// Note that PLIC asserts that this is > 0. case IncludeJtagDTM => false
case IncludeJtagDTM => false case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4) case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4) case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2) case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock })
case _ => throw new CDEMatchError
})
class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig) class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig) class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
@ -46,32 +44,21 @@ class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
class DefaultBufferlessConfig extends Config( class DefaultBufferlessConfig extends Config(
new WithBufferlessBroadcastHub ++ new BaseConfig) new WithBufferlessBroadcastHub ++ new BaseConfig)
class FPGAConfig extends Config ( class FPGAConfig extends Config ((site, here, up) => {
(pname,site,here) => pname match { case NAcquireTransactors => 4
case NAcquireTransactors => 4 })
case _ => throw new CDEMatchError
}
)
class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig) class DefaultFPGAConfig extends Config(new FPGAConfig ++ new BaseConfig)
class DefaultL2FPGAConfig extends Config( class DefaultL2FPGAConfig extends Config(
new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig) new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config) class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n)
})
class WithNMemoryChannels(n: Int) extends Config( class WithExtMemSize(n: Long) extends Config((site, here, up) => {
(pname,site,here,up) => pname match { case ExtMem => up(ExtMem, site).copy(size = n)
case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n) })
case _ => throw new CDEMatchError
}
)
class WithExtMemSize(n: Long) extends Config(
(pname,site,here,up) => pname match {
case ExtMem => up(ExtMem, site).copy(size = n)
case _ => throw new CDEMatchError
}
)
class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384)) class WithScratchpads extends Config(new WithNMemoryChannels(0) ++ new WithDataScratchpad(16384))
@ -97,11 +84,9 @@ class DualChannelDualBankL2Config extends Config(
class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig) class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
class WithEdgeDataBits(dataBits: Int) extends Config( class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
(pname, site, here, up) => pname match { case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8) })
case _ => throw new CDEMatchError
})
class Edge128BitConfig extends Config( class Edge128BitConfig extends Config(
new WithEdgeDataBits(128) ++ new BaseConfig) new WithEdgeDataBits(128) ++ new BaseConfig)
@ -127,48 +112,30 @@ class TinyConfig extends Config(
new WithSmallCores ++ new WithRV32 ++ new WithSmallCores ++ new WithRV32 ++
new WithStatelessBridge ++ new BaseConfig) new WithStatelessBridge ++ new BaseConfig)
class WithJtagDTM extends Config ( class WithJtagDTM extends Config ((site, here, up) => {
(pname, site, here) => pname match { case IncludeJtagDTM => true
case IncludeJtagDTM => true })
case _ => throw new CDEMatchError
}
)
class WithNoPeripheryArithAMO extends Config ( class WithNoPeripheryArithAMO extends Config ((site, here, up) => {
(pname, site, here) => pname match { case PeripheryBusArithmetic => false
case PeripheryBusArithmetic => false })
}
)
class With64BitPeriphery extends Config ( class With64BitPeriphery extends Config ((site, here, up) => {
(pname, site, here) => pname match { case PeripheryBusConfig => TLBusConfig(beatBytes = 8)
case PeripheryBusConfig => TLBusConfig(beatBytes = 8) })
}
)
class WithoutTLMonitors extends Config ( class WithoutTLMonitors extends Config ((site, here, up) => {
(pname, site, here) => pname match { case TLMonitorBuilder => (args: TLMonitorArgs) => None
case TLMonitorBuilder => (args: TLMonitorArgs) => None })
case _ => throw new CDEMatchError
}
)
class WithNExtTopInterrupts(nExtInts: Int) extends Config( class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
(pname, site, here) => pname match { case NExtTopInterrupts => nExtInts
case NExtTopInterrupts => nExtInts })
case _ => throw new CDEMatchError
}
)
class WithNBreakpoints(hwbp: Int) extends Config ( class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
(pname,site,here) => pname match { case NBreakpoints => hwbp
case NBreakpoints => hwbp })
case _ => throw new CDEMatchError
}
)
class WithRTCPeriod(nCycles: Int) extends Config( class WithRTCPeriod(nCycles: Int) extends Config((site, here, up) => {
(pname, site, here) => pname match { case RTCPeriod => nCycles
case RTCPeriod => nCycles })
case _ => throw new CDEMatchError
})

122
src/main/scala/unittest/Configs.scala
View File

@ -7,79 +7,71 @@ import config._
import junctions._ import junctions._
import rocketchip.{BaseConfig, BasePlatformConfig} import rocketchip.{BaseConfig, BasePlatformConfig}
class WithJunctionsUnitTests extends Config( class WithJunctionsUnitTests extends Config((site, here, up) => {
(pname, site, here) => pname match { case HastiId => "HastiTest"
case HastiId => "HastiTest" case HastiKey("HastiTest") => HastiParameters(addrBits = 32, dataBits = 64)
case HastiKey("HastiTest") => HastiParameters(addrBits = 32, dataBits = 64) case NastiKey => NastiParameters(addrBits = 32, dataBits = 64, idBits = 4)
case NastiKey => NastiParameters(addrBits = 32, dataBits = 64, idBits = 4) case junctions.PAddrBits => 32
case junctions.PAddrBits => 32 case rocket.XLen => 64
case rocket.XLen => 64 case UnitTests => (p: Parameters) => Seq(
case UnitTests => (p: Parameters) => Seq( Module(new junctions.MultiWidthFifoTest),
Module(new junctions.MultiWidthFifoTest), Module(new junctions.HastiTest()(p)))
Module(new junctions.HastiTest()(p))) })
case _ => throw new CDEMatchError
})
class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new BasePlatformConfig) class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new BasePlatformConfig)
class WithUncoreUnitTests extends Config( class WithUncoreUnitTests extends Config((site, here, up) => {
(pname, site, here) => pname match { case uncore.tilelink.TLId => "L1toL2"
case uncore.tilelink.TLId => "L1toL2" case UnitTests => (q: Parameters) => {
case UnitTests => (q: Parameters) => { implicit val p = q
implicit val p = q Seq(
Seq( Module(new uncore.devices.ROMSlaveTest()),
Module(new uncore.devices.ROMSlaveTest()), Module(new uncore.devices.TileLinkRAMTest()),
Module(new uncore.devices.TileLinkRAMTest()), Module(new uncore.converters.TileLinkWidthAdapterTest()),
Module(new uncore.converters.TileLinkWidthAdapterTest()), Module(new uncore.tilelink2.TLFuzzRAMTest),
Module(new uncore.tilelink2.TLFuzzRAMTest), Module(new uncore.ahb.AHBBridgeTest),
Module(new uncore.ahb.AHBBridgeTest), Module(new uncore.apb.APBBridgeTest),
Module(new uncore.apb.APBBridgeTest), Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
Module(new uncore.axi4.AXI4LiteFuzzRAMTest), Module(new uncore.axi4.AXI4FullFuzzRAMTest),
Module(new uncore.axi4.AXI4FullFuzzRAMTest), Module(new uncore.axi4.AXI4BridgeTest)) }
Module(new uncore.axi4.AXI4BridgeTest)) } })
case _ => throw new CDEMatchError
}
)
class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseConfig) class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseConfig)
class WithTLSimpleUnitTests extends Config( class WithTLSimpleUnitTests extends Config((site, here, up) => {
(pname, site, here) => pname match { case UnitTests => (q: Parameters) => {
case UnitTests => (q: Parameters) => { implicit val p = q
implicit val p = q Seq(
Seq( Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
Module(new uncore.tilelink2.TLRAMSimpleTest(1)), Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
Module(new uncore.tilelink2.TLRAMSimpleTest(4)), Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
Module(new uncore.tilelink2.TLRAMSimpleTest(16)), Module(new uncore.tilelink2.TLRR0Test),
Module(new uncore.tilelink2.TLRR0Test), Module(new uncore.tilelink2.TLRR1Test),
Module(new uncore.tilelink2.TLRR1Test), Module(new uncore.tilelink2.TLRAMCrossingTest) ) }
Module(new uncore.tilelink2.TLRAMCrossingTest) ) } })
case _ => throw new CDEMatchError })
class WithTLWidthUnitTests extends Config( class WithTLWidthUnitTests extends Config((site, here, up) => {
(pname, site, here) => pname match { case UnitTests => (q: Parameters) => {
case UnitTests => (q: Parameters) => { implicit val p = q
implicit val p = q Seq(
Seq( Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)), Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)),
Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)), Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)),
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)), Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1)), Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)),
Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)), Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4)) ) }
Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4)) ) } })
case _ => throw new CDEMatchError })
class WithTLXbarUnitTests extends Config( class WithTLXbarUnitTests extends Config((site, here, up) => {
(pname, site, here) => pname match { case UnitTests => (q: Parameters) => {
case UnitTests => (q: Parameters) => { implicit val p = q
implicit val p = q Seq(
Seq( Module(new uncore.tilelink2.TLRAMXbarTest(1)),
Module(new uncore.tilelink2.TLRAMXbarTest(1)), Module(new uncore.tilelink2.TLRAMXbarTest(2)),
Module(new uncore.tilelink2.TLRAMXbarTest(2)), Module(new uncore.tilelink2.TLRAMXbarTest(8)),
Module(new uncore.tilelink2.TLRAMXbarTest(8)), //Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)),
//Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)), Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) }
Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) } })
case _ => throw new CDEMatchError })
class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new BasePlatformConfig) class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new BasePlatformConfig)
class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new BasePlatformConfig) class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new BasePlatformConfig)