Configs: use a uniform syntax without Match exceptions (#507)
* Configs: use a uniform syntax without Match exceptions The old style of specifying Configs used total functions. The only way to indicate that a key was not matched was to throw an exception. Not only was this a performance concern, but it also caused confusing error messages whenever you had a match failure from a lookup within a lookup. The exception could get handled by an outer-lookup that then reported the wrong key as missing.
This commit is contained in:
Wesley W. Terpstra
committed by
Henry Cook
Henry Cook
parent
b448387899
commit
52bb6cd9d9
@ -7,79 +7,71 @@ import config._
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import junctions._
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import rocketchip.{BaseConfig, BasePlatformConfig}
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class WithJunctionsUnitTests extends Config(
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(pname, site, here) => pname match {
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case HastiId => "HastiTest"
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case HastiKey("HastiTest") => HastiParameters(addrBits = 32, dataBits = 64)
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case NastiKey => NastiParameters(addrBits = 32, dataBits = 64, idBits = 4)
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case junctions.PAddrBits => 32
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case rocket.XLen => 64
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case UnitTests => (p: Parameters) => Seq(
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Module(new junctions.MultiWidthFifoTest),
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Module(new junctions.HastiTest()(p)))
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case _ => throw new CDEMatchError
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})
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class WithJunctionsUnitTests extends Config((site, here, up) => {
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case HastiId => "HastiTest"
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case HastiKey("HastiTest") => HastiParameters(addrBits = 32, dataBits = 64)
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case NastiKey => NastiParameters(addrBits = 32, dataBits = 64, idBits = 4)
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case junctions.PAddrBits => 32
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case rocket.XLen => 64
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case UnitTests => (p: Parameters) => Seq(
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Module(new junctions.MultiWidthFifoTest),
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Module(new junctions.HastiTest()(p)))
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})
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class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new BasePlatformConfig)
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class WithUncoreUnitTests extends Config(
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(pname, site, here) => pname match {
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case uncore.tilelink.TLId => "L1toL2"
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.devices.ROMSlaveTest()),
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Module(new uncore.devices.TileLinkRAMTest()),
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Module(new uncore.converters.TileLinkWidthAdapterTest()),
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Module(new uncore.tilelink2.TLFuzzRAMTest),
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Module(new uncore.ahb.AHBBridgeTest),
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Module(new uncore.apb.APBBridgeTest),
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Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
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Module(new uncore.axi4.AXI4FullFuzzRAMTest),
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Module(new uncore.axi4.AXI4BridgeTest)) }
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case _ => throw new CDEMatchError
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}
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)
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class WithUncoreUnitTests extends Config((site, here, up) => {
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case uncore.tilelink.TLId => "L1toL2"
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.devices.ROMSlaveTest()),
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Module(new uncore.devices.TileLinkRAMTest()),
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Module(new uncore.converters.TileLinkWidthAdapterTest()),
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Module(new uncore.tilelink2.TLFuzzRAMTest),
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Module(new uncore.ahb.AHBBridgeTest),
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Module(new uncore.apb.APBBridgeTest),
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Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
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Module(new uncore.axi4.AXI4FullFuzzRAMTest),
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Module(new uncore.axi4.AXI4BridgeTest)) }
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})
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class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseConfig)
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class WithTLSimpleUnitTests extends Config(
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(pname, site, here) => pname match {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
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Module(new uncore.tilelink2.TLRR0Test),
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Module(new uncore.tilelink2.TLRR1Test),
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Module(new uncore.tilelink2.TLRAMCrossingTest) ) }
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case _ => throw new CDEMatchError })
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class WithTLSimpleUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
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Module(new uncore.tilelink2.TLRAMSimpleTest(16)),
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Module(new uncore.tilelink2.TLRR0Test),
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Module(new uncore.tilelink2.TLRR1Test),
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Module(new uncore.tilelink2.TLRAMCrossingTest) ) }
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})
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class WithTLWidthUnitTests extends Config(
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(pname, site, here) => pname match {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4)) ) }
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case _ => throw new CDEMatchError })
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class WithTLWidthUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)),
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Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 1, 1)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest( 4, 64)),
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Module(new uncore.tilelink2.TLRAMWidthWidgetTest(64, 4)) ) }
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})
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class WithTLXbarUnitTests extends Config(
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(pname, site, here) => pname match {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMXbarTest(1)),
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Module(new uncore.tilelink2.TLRAMXbarTest(2)),
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Module(new uncore.tilelink2.TLRAMXbarTest(8)),
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//Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)),
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Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) }
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case _ => throw new CDEMatchError })
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class WithTLXbarUnitTests extends Config((site, here, up) => {
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case UnitTests => (q: Parameters) => {
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implicit val p = q
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Seq(
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Module(new uncore.tilelink2.TLRAMXbarTest(1)),
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Module(new uncore.tilelink2.TLRAMXbarTest(2)),
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Module(new uncore.tilelink2.TLRAMXbarTest(8)),
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//Module(new uncore.tilelink2.TLMulticlientXbarTest(4,4)),
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Module(new uncore.tilelink2.TLMulticlientXbarTest(1,4)) ) }
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})
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class TLSimpleUnitTestConfig extends Config(new WithTLSimpleUnitTests ++ new BasePlatformConfig)
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class TLWidthUnitTestConfig extends Config(new WithTLWidthUnitTests ++ new BasePlatformConfig)
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