riscv/rocket-chip
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Keep io.cpu.s1_data for visibility (#1218)

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solomatnikov 2018-01-31 14:31:42 -08:00 committed by GitHub
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commit 5294523551
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src/main/scala/rocket/HellaCache.scala
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@ -186,6 +186,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
val (tl_out, _) = outer.node.out(0) val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle(outer)) val io = IO(new HellaCacheBundle(outer))
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
dontTouch(io.cpu.s1_data)
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
fifoManagers.foreach { m => fifoManagers.foreach { m =>