From cedfb0e784d4a6fac5346a77e7fc1ad069948b7d Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 2 Oct 2017 17:41:52 -0700 Subject: [PATCH 1/3] coreplex: dontTouch the rocket_tile_inputs wire which contains hartid. --- src/main/scala/coreplex/RocketCoreplex.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index b4992a3c..e0db5333 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -3,6 +3,7 @@ package freechips.rocketchip.coreplex import Chisel._ +import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} @@ -110,9 +111,9 @@ trait HasRocketTilesModuleImp extends LazyModuleImp // TODO make this less gross and/or support tiles with differently sized reset vectors def resetVectorBits: Int = outer.paddrBits - val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { + val rocket_tile_inputs = dontTouch(Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial { case SharedMemoryTLEdge => outer.sharedMemoryTLEdge - }))) + })))) // dontTouch keeps constant prop from sucking these signals into the tile // Unconditionally wire up the non-diplomatic tile inputs outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) => @@ -126,7 +127,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp rocket_tile_inputs.zipWithIndex.foreach { case(wire, i) => wire.clock := clock wire.reset := reset - wire.hartid := UInt(i) + wire.hartid := i.U wire.reset_vector := global_reset_vector } } From aa3a18222c9a3348e4ffe9543d9cacd3ca468273 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 2 Oct 2017 19:01:05 -0700 Subject: [PATCH 2/3] HellaCache: users like to peep resp.data and resp.addr --- src/main/scala/rocket/HellaCache.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 558e0259..ae316ee4 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.rocket import Chisel._ +import chisel3.experimental.dontTouch import freechips.rocketchip.config.{Parameters, Field} import freechips.rocketchip.coreplex._ import freechips.rocketchip.diplomacy._ @@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) implicit val edge = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle(outer)) + dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable) fifoManagers.foreach { m => From d33737802a0678a1d284dfcea057e799ef897ab9 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 2 Oct 2017 19:34:51 -0700 Subject: [PATCH 3/3] util: add DontTouch trait with dontTouchPorts method --- src/main/scala/system/ExampleRocketSystem.scala | 2 ++ src/main/scala/system/TestHarness.scala | 1 + src/main/scala/util/Misc.scala | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/src/main/scala/system/ExampleRocketSystem.scala b/src/main/scala/system/ExampleRocketSystem.scala index f15c297b..981f7a0d 100644 --- a/src/main/scala/system/ExampleRocketSystem.scala +++ b/src/main/scala/system/ExampleRocketSystem.scala @@ -6,6 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.coreplex._ import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.util.DontTouch /** Example Top with periphery devices and ports, and a Rocket coreplex */ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex @@ -25,3 +26,4 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro with HasMasterAXI4MMIOPortModuleImp with HasSlaveAXI4PortModuleImp with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/src/main/scala/system/TestHarness.scala b/src/main/scala/system/TestHarness.scala index e8accb7f..79903b32 100644 --- a/src/main/scala/system/TestHarness.scala +++ b/src/main/scala/system/TestHarness.scala @@ -14,6 +14,7 @@ class TestHarness()(implicit p: Parameters) extends Module { val dut = Module(LazyModule(new ExampleRocketSystem).module) dut.reset := reset | dut.debug.ndreset + dut.dontTouchPorts() dut.tieOffInterrupts() dut.connectSimAXIMem() dut.connectSimAXIMMIO() diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index 86590d1b..8ff24fb9 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.util import Chisel._ +import chisel3.experimental.{dontTouch, RawModule} import freechips.rocketchip.config.Parameters import scala.math._ @@ -21,6 +22,21 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle { } } +// TODO: replace this with an implicit class when @chisel unprotects dontTouchPorts +trait DontTouch { + self: RawModule => + + /** Marks every port as don't touch + * + * @note This method can only be called after the Module has been fully constructed + * (after Module(...)) + */ + def dontTouchPorts(): this.type = { + self.getModulePorts.foreach(dontTouch(_)) + self + } +} + trait Clocked extends Bundle { val clock = Clock() val reset = Bool()