riscv/rocket-chip
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This commit is contained in:
Christopher Celio 2015-04-12 18:44:03 -07:00
parent 4d6ebded02
commit 517d0d4b89
1 changed files with 5 additions and 7 deletions
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12
rocket/src/main/scala/icache.scala
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@ -114,13 +114,11 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid)
io.cpu.resp.bits.pc := s2_pc io.cpu.resp.bits.pc := s2_pc
var fetch_data:Bits = null require(coreFetchWidth * coreInstBytes <= rowBytes)
require (coreFetchWidth <= 4) val fetch_data =
if (coreFetchWidth == 4) { if (coreFetchWidth * coreInstBytes == rowBytes) icache.io.resp.bits.datablock
fetch_data = icache.io.resp.bits.datablock else icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
} else {
fetch_data = icache.io.resp.bits.datablock >> (s2_pc(log2Up(rowBytes)-1,log2Up(coreFetchWidth*coreInstBytes)) << log2Up(coreFetchWidth*coreInstBits))
}
for (i <- 0 until coreFetchWidth) { for (i <- 0 until coreFetchWidth) {
io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits) io.cpu.resp.bits.data(i) := fetch_data(i*coreInstBits+coreInstBits-1, i*coreInstBits)
} }