Improve back-to-back integer multiplication performance
More exact hazard checking in the decode stage avoids a pipeline flush.
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7b69f1f261
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@ -465,6 +465,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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wb_reg_pc := mem_reg_pc
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}
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val wb_wxd = wb_reg_valid && wb_ctrl.wxd
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val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc
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val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
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val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
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@ -479,12 +480,12 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
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val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
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div.io.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
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div.io.resp.ready := !wb_wxd
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val ll_wdata = Wire(init = div.io.resp.bits.data)
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val ll_waddr = Wire(init = div.io.resp.bits.tag)
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val ll_wen = Wire(init = div.io.resp.fire())
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if (usingRoCC) {
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io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd)
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io.rocc.resp.ready := !wb_wxd
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when (io.rocc.resp.fire()) {
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div.io.resp.ready := Bool(false)
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ll_wdata := io.rocc.resp.bits.data
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@ -581,6 +582,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
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id_ctrl.fp && id_stall_fpu ||
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id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
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id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
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id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay
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id_do_fence ||
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csr.io.csr_stall
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ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
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