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axi4: RegisterRouter supports user bits

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This commit is contained in:
Wesley W. Terpstra 2017-04-20 17:58:07 -07:00
parent de6ea9b442
commit 5163ccd11f
1 changed files with 10 additions and 5 deletions
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15
src/main/scala/uncore/axi4/RegisterRouter.scala
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@ -30,7 +30,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
val r = bundleIn(0).r val r = bundleIn(0).r
val b = bundleIn(0).b val b = bundleIn(0).b
val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, ar.bits.params.idBits) val params = RegMapperParams(log2Up((address.mask+1)/beatBytes), beatBytes, ar.bits.params.idBits + ar.bits.params.userBits)
val in = Wire(Decoupled(new RegMapperInput(params))) val in = Wire(Decoupled(new RegMapperInput(params)))
// Prefer to execute reads first // Prefer to execute reads first
@ -39,15 +39,17 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
aw.ready := in.ready && !ar.valid && w .valid aw.ready := in.ready && !ar.valid && w .valid
w .ready := in.ready && !ar.valid && aw.valid w .ready := in.ready && !ar.valid && aw.valid
val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr) val ar_extra = Cat(Seq(ar.bits.id) ++ ar.bits.user.toList)
val in_id = Mux(ar.valid, ar.bits.id, aw.bits.id) val aw_extra = Cat(Seq(aw.bits.id) ++ aw.bits.user.toList)
val in_extra = Mux(ar.valid, ar_extra, aw_extra)
val addr = Mux(ar.valid, ar.bits.addr, aw.bits.addr)
val mask = uncore.tilelink2.maskGen(ar.bits.addr, ar.bits.size, beatBytes) val mask = uncore.tilelink2.maskGen(ar.bits.addr, ar.bits.size, beatBytes)
in.bits.read := ar.valid in.bits.read := ar.valid
in.bits.index := addr >> log2Ceil(beatBytes) in.bits.index := addr >> log2Ceil(beatBytes)
in.bits.data := w.bits.data in.bits.data := w.bits.data
in.bits.mask := Mux(ar.valid, mask, w.bits.strb) in.bits.mask := Mux(ar.valid, mask, w.bits.strb)
in.bits.extra := in_id in.bits.extra := in_extra
// Invoke the register map builder and make it Irrevocable // Invoke the register map builder and make it Irrevocable
val out = Queue.irrevocable( val out = Queue.irrevocable(
@ -59,14 +61,17 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
r.valid := out.valid && out.bits.read r.valid := out.valid && out.bits.read
b.valid := out.valid && !out.bits.read b.valid := out.valid && !out.bits.read
val out_id = if (r.bits.params.idBits == 0) UInt(0) else out.bits.extra val out_id = if (r.bits.params.idBits == 0) UInt(0) else (out.bits.extra >> ar.bits.params.userBits)
r.bits.id := out_id r.bits.id := out_id
r.bits.data := out.bits.data r.bits.data := out.bits.data
r.bits.last := Bool(true) r.bits.last := Bool(true)
r.bits.resp := AXI4Parameters.RESP_OKAY r.bits.resp := AXI4Parameters.RESP_OKAY
r.bits.user.foreach { _ := out.bits.extra }
b.bits.id := out_id b.bits.id := out_id
b.bits.resp := AXI4Parameters.RESP_OKAY b.bits.resp := AXI4Parameters.RESP_OKAY
b.bits.user.foreach { _ := out.bits.extra }
} }
} }