riscv/rocket-chip
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Fix typo in breakpoint cover property.

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Richard Xia 2017-12-04 14:04:24 -08:00
parent b8098d18be
commit 50de991f18
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/RocketCore.scala
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@ -438,7 +438,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val memCoverCauses = (exCoverCauses ++ List( val memCoverCauses = (exCoverCauses ++ List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"), (CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREKPOINT"), (Causes.breakpoint, "BREAKPOINT"),
(Causes.misaligned_fetch, "MISALIGNED_FETCH") (Causes.misaligned_fetch, "MISALIGNED_FETCH")
)).distinct )).distinct
coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses)