riscv/rocket-chip
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replace RDNPC with AUIPC

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This commit is contained in:
Andrew Waterman 2013-04-22 04:20:15 -07:00
parent db5a060c7d
commit 50ccc20bf3
3 changed files with 7 additions and 6 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -97,7 +97,7 @@ object XDecode extends DecodeConstants
JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), JALR_C-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N),
JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), JALR_J-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N),
JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), JALR_R-> List(Y, N,N,BR_N, Y,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N),
RDNPC-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N), AUIPC-> List(Y, N,N,BR_N, N,N,N,A2_LTYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,N,Y,WA_RD,WB_PC, PCR.N,N,N,N,N,N),
LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), LB-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),
LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N), LH-> List(Y, N,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,WA_RD,WB_ALU,PCR.N,N,N,N,N,N),

10
rocket/src/main/scala/dpath.scala
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@ -214,15 +214,15 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2, Mux(io.ctrl.ex_br_type === BR_GEU, ex_rs1 >= ex_rs2,
io.ctrl.ex_br_type === BR_J)))))) io.ctrl.ex_br_type === BR_J))))))
val ex_pc_plus4 = ex_reg_pc + 4 val ex_pc_plus4 = ex_reg_pc.toFix + Mux(ex_reg_sel_alu2 === A2_LTYPE, ex_reg_inst(26,7).toFix << 12, Fix(4))
val ex_branch_target = (ex_reg_pc.toFix + (ex_imm << 1)).toUFix val ex_branch_target = ex_reg_pc.toFix + (ex_imm << 1)
val tsc_reg = WideCounter(64) val tsc_reg = WideCounter(64)
val irt_reg = WideCounter(64, io.ctrl.wb_valid) val irt_reg = WideCounter(64, io.ctrl.wb_valid)
// writeback select mux // writeback select mux
val ex_wdata = val ex_wdata =
Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4.toFix, Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_pc_plus4,
Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value, Mux(ex_reg_ctrl_sel_wb === WB_TSC, tsc_reg.value,
Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value, Mux(ex_reg_ctrl_sel_wb === WB_IRT, irt_reg.value,
alu.io.out))).toBits // WB_ALU alu.io.out))).toBits // WB_ALU
@ -328,8 +328,8 @@ class Datapath(implicit conf: RocketConfiguration) extends Component
io.imem.req.bits.pc := io.imem.req.bits.pc :=
Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4, Mux(io.ctrl.sel_pc === PC_EX4, ex_pc_plus4,
Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target), Mux(io.ctrl.sel_pc === PC_EX, Mux(io.ctrl.ex_jalr, ex_effective_address, ex_branch_target),
Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec).toUFix, Mux(io.ctrl.sel_pc === PC_PCR, Cat(pcr.io.evec(VADDR_BITS-1), pcr.io.evec),
wb_reg_pc))) // PC_WB wb_reg_pc))).toUFix // PC_WB
// expose debug signals to testbench // expose debug signals to testbench
// XXX debug() doesn't right, so create a false dependence // XXX debug() doesn't right, so create a false dependence

1
rocket/src/main/scala/instructions.scala
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@ -20,6 +20,7 @@ object Instructions
val BLTU = Bits("b?????_?????_?????_???????_110_1100011",32); val BLTU = Bits("b?????_?????_?????_???????_110_1100011",32);
val BGEU = Bits("b?????_?????_?????_???????_111_1100011",32); val BGEU = Bits("b?????_?????_?????_???????_111_1100011",32);
val LUI = Bits("b?????_????????????????????_0110111",32); val LUI = Bits("b?????_????????????????????_0110111",32);
val AUIPC = Bits("b?????_????????????????????_0010111",32);
val ADDI = Bits("b?????_?????_????????????_000_0010011",32); val ADDI = Bits("b?????_?????_????????????_000_0010011",32);
val SLLI = Bits("b?????_?????_000000_??????_001_0010011",32); val SLLI = Bits("b?????_?????_000000_??????_001_0010011",32);
val SLTI = Bits("b?????_?????_????????????_010_0010011",32); val SLTI = Bits("b?????_?????_????????????_010_0010011",32);