riscv/rocket-chip
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TLXbar: Allow more masters and slaves and issue a warning.

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This commit is contained in:
Megan Wachs 2017-08-03 15:39:18 -07:00
parent 1be1433f04
commit 50c85f1b62
1 changed files with 7 additions and 2 deletions
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9
src/main/scala/tilelink/Xbar.scala
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@ -9,8 +9,8 @@ import freechips.rocketchip.diplomacy._
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule
{ {
val node = TLNexusNode( val node = TLNexusNode(
numClientPorts = 1 to 32, numClientPorts = 1 to 999,
numManagerPorts = 1 to 32, numManagerPorts = 1 to 999,
clientFn = { seq => clientFn = { seq =>
require (!seq.exists(_.unsafeAtomics) || seq.size == 1, require (!seq.exists(_.unsafeAtomics) || seq.size == 1,
"An unsafe atomic port can not be combined with any other!") "An unsafe atomic port can not be combined with any other!")
@ -46,6 +46,11 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
val out = node.bundleOut val out = node.bundleOut
} }
if ((io.in.size * io.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name) is very large, with ${io.in.size} Masters and ${io.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
// Grab the port ID mapping // Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(node.edgesIn.map(_.client)) val inputIdRanges = TLXbar.mapInputIds(node.edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(node.edgesOut.map(_.manager)) val outputIdRanges = TLXbar.mapOutputIds(node.edgesOut.map(_.manager))