riscv/rocket-chip
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DebugModule: Be more paranoid about addressing corner cases.

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This commit is contained in:
Megan Wachs 2016-10-26 18:03:07 -07:00 committed by Wesley W. Terpstra
parent b99662796d
commit 5090ff945b
1 changed files with 5 additions and 5 deletions
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10
src/main/scala/uncore/devices/Debug.scala
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@ -480,6 +480,9 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
val dbRamRdEn = Wire(Bool())
val dbRamWrEnFinal = Wire(Bool())
val dbRamRdEnFinal = Wire(Bool())
require((cfg.nDebugRamBytes % ramDataBytes) == 0)
val dbRamDataOffset = log2Up(ramDataBytes)
// --- Debug Bus Accesses
@ -606,10 +609,7 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
// 0x40 - 0x6F Not Implemented
dbRamAddr := dbReq.addr( ramAddrWidth-1 , 0)
dbRamWrData := dbReq.data
dbRamAddrValid := Bool(true)
if (ramAddrWidth < 4){
dbRamAddrValid := (dbReq.addr(3, ramAddrWidth) === UInt(0))
}
dbRamAddrValid := (dbReq.addr(3,0) <= UInt((cfg.nDebugRamBytes/ramDataBytes)))
val dbRamRdDataFields = List.tabulate(cfg.nDebugRamBytes / ramDataBytes) { ii =>
val slice = ramMem.slice(ii * ramDataBytes, (ii+1)*ramDataBytes)
@ -620,7 +620,7 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
when (dbRamWrEnFinal) {
for (ii <- 0 until ramDataBytes) {
ramMem(dbRamAddr * UInt(ramDataBytes) + UInt(ii)) := dbRamWrData((8*(ii+1)-1), (8*ii))
ramMem((dbRamAddr << UInt(dbRamDataOffset)) + UInt(ii)) := dbRamWrData((8*(ii+1)-1), (8*ii))
}
}