util: dontTouch work-around for zero width aggregates
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@ -4,7 +4,7 @@
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package freechips.rocketchip.util
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package freechips.rocketchip.util
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import Chisel._
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import Chisel._
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import chisel3.experimental.{dontTouch, RawModule}
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import chisel3.experimental.{ChiselAnnotation, RawModule}
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.config.Parameters
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import scala.math._
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import scala.math._
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@ -26,6 +26,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle {
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trait DontTouch {
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trait DontTouch {
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self: RawModule =>
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self: RawModule =>
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def dontTouch(data: Data): Unit = data match {
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case agg: Aggregate =>
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agg.getElements.foreach(dontTouch)
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case elt: Element =>
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annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!"))
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}
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/** Marks every port as don't touch
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/** Marks every port as don't touch
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*
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*
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* @note This method can only be called after the Module has been fully constructed
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* @note This method can only be called after the Module has been fully constructed
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